coreboot-gerrit April 2018

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Change in coreboot[master]: soc/amd: Add "halt this AP" callback to romstage
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25527 ) Change subject: soc/amd: Add "halt this AP" callback to romstage ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69804/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24092/ : SUCCESS -- To view, visit https://review.coreboot.org/25527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0992b2de5856881c19191ec4f637168727686524 Gerrit-Change-Number: 25527 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 22:51:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard: Make OemCustomize.c available at romstage
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25528 ) Change subject: mainboard: Make OemCustomize.c available at romstage ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69802/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24091/ : SUCCESS -- To view, visit https://review.coreboot.org/25528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Gerrit-Change-Number: 25528 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshall.dawson(a)scarletltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 22:46:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel: Remove superfluous pointers variables
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25572 Change subject: soc/intel: Remove superfluous pointers variables ...................................................................... soc/intel: Remove superfluous pointers variables Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/ebda/ebda.c M src/soc/intel/skylake/memmap.c 3 files changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/25572/1 diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 0636b08..108a1b0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -316,7 +316,6 @@ void *cbmem_top(void) { struct ebda_config ebda_cfg; - struct ebda_config *cfg = &ebda_cfg; /* * Check if Tseg has been initialized, we will use this as a flag @@ -327,7 +326,7 @@ if (sa_get_tseg_base() == 0) return NULL; - retrieve_ebda_object(cfg); + retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)cfg->tolum_base; + return (void *)(uintptr_t)ebda_cfg.tolum_base; } diff --git a/src/soc/intel/common/block/ebda/ebda.c b/src/soc/intel/common/block/ebda/ebda.c index 4f60490..d16ad6e 100644 --- a/src/soc/intel/common/block/ebda/ebda.c +++ b/src/soc/intel/common/block/ebda/ebda.c @@ -40,13 +40,12 @@ void fill_ebda_area(void) { struct ebda_config ebda_cfg; - struct ebda_config *cfg = &ebda_cfg; /* Initialize EBDA area early during romstage. */ setup_default_ebda(); - create_soc_ebda(cfg); - create_mainboard_ebda(cfg); - write_ebda_data(cfg, sizeof(*cfg)); + create_soc_ebda(&ebda_cfg); + create_mainboard_ebda(&ebda_cfg); + write_ebda_data(&ebda_cfg, sizeof(ebda_cfg)); } void retrieve_ebda_object(struct ebda_config *cfg) diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9151d96..f0ccb1d 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -338,7 +338,6 @@ void *cbmem_top(void) { struct ebda_config ebda_cfg; - struct ebda_config *cfg = &ebda_cfg; /* * Check if Tseg has been initialized, we will use this as a flag @@ -349,7 +348,7 @@ if (sa_get_tseg_base() == 0) return NULL; - retrieve_ebda_object(cfg); + retrieve_ebda_object(&ebda_cfg); - return (void *)(uintptr_t)cfg->tolum_base; + return (void *)(uintptr_t)ebda_cfg.tolum_base; } -- To view, visit https://review.coreboot.org/25572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Gerrit-Change-Number: 25572 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: Documentation: Fix a bunch of typos
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/25571 ) Change subject: Documentation: Fix a bunch of typos ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/25571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Gerrit-Change-Number: 25571 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 20:59:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Fix a bunch of typos
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25571 ) Change subject: Documentation: Fix a bunch of typos ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69783/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24072/ : SUCCESS -- To view, visit https://review.coreboot.org/25571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Gerrit-Change-Number: 25571 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 20:53:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation: Fix a bunch of typos
by Jonathan Neuschäfer (Code Review) 10 Apr '18

10 Apr '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25571 Change subject: Documentation: Fix a bunch of typos ...................................................................... Documentation: Fix a bunch of typos Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M Documentation/Intel/NativeRaminit/SandyBridge_registers.md M Documentation/Lesson2.md M Documentation/RFC/chip.tex M Documentation/cbfs.txt M Documentation/corebootBuildingGuide.tex 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/25571/1 diff --git a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md index 2dce11b..c961890 100644 --- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md +++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md @@ -966,7 +966,7 @@ *Width:* 24 Bit -*Desc:* TC_DBP - Timming of DDR - Bin Parameter Register, Channel 0 +*Desc:* TC_DBP - Timing of DDR - Bin Parameter Register, Channel 0 |Bit| Description | |---|-------------| diff --git a/Documentation/Lesson2.md b/Documentation/Lesson2.md index 0263ced..ec929c8 100644 --- a/Documentation/Lesson2.md +++ b/Documentation/Lesson2.md @@ -20,7 +20,7 @@ <https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/us…)> and follow the instructions there. Then, skip to Part 3. -Additonally, that section of the Web site provides explanation on starting +Additionally, that section of the Web site provides explanation on starting an ssh-agent, which may be particularly helpful for those who anticipate frequently uploading changes. @@ -110,7 +110,7 @@ git commit -s -**Note:** The -s adds a signed-off-by line by the commiter. Your commit should be +**Note:** The -s adds a signed-off-by line by the committer. Your commit should be signed off with your name and email (i.e. **Your Name** **<Your Email>**, based on what you set with git config earlier). @@ -236,7 +236,7 @@ git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1 **Note:** cd will change your directory to your home directory, so the -git clone commmand will be run there. +git clone command will be run there. Finally, open the ~/.bashrc file and append the following two lines: diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex index 5e366b8..01f40c1 100644 --- a/Documentation/RFC/chip.tex +++ b/Documentation/RFC/chip.tex @@ -14,7 +14,7 @@ \section{Goals} The goals of the new chip architecture are these: \begin{itemize} -\item seperate implementation details from specification in the Config file +\item separate implementation details from specification in the Config file (translation: no more C code in Config files) \item make the specification easier for people to use and understand \item remove private details of a given chip to the chip file as much @@ -223,7 +223,7 @@ const char *value; }; -These get filled in by the config tool as before. The linuxbios libary can +These get filled in by the config tool as before. The linuxbios library can then provide a generic parsing function for the superios to use. The remaining question is how should the superio command look in diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt index 6c5c228..7adae61 100644 --- a/Documentation/cbfs.txt +++ b/Documentation/cbfs.txt @@ -36,7 +36,7 @@ The header on each "file" (or component, as I like to style them) has been simplified - We now only store the length, the type, the checksum, and the offset to the data. The name scheme remains the same. The -addtional information, which is component specific, has been moved to +additional information, which is component specific, has been moved to the component itself (see below). The components are arranged in the ROM aligned along the specified @@ -245,7 +245,7 @@ | ... | \--------/ <- start + 'offset' + 'len' -== Searching Alogrithm == +== Searching Algorithm == To locate a specific component in the ROM, one starts at the 'offset' specified in the CBFS master header. For this example, the offset will @@ -379,7 +379,7 @@ PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data -PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment +PAYLOAD_SEGMENT_BSS 0x20535342 The memory specified by the segment should be zeroed PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for the payload diff --git a/Documentation/corebootBuildingGuide.tex b/Documentation/corebootBuildingGuide.tex index 867891b..e451ad4 100644 --- a/Documentation/corebootBuildingGuide.tex +++ b/Documentation/corebootBuildingGuide.tex @@ -413,8 +413,8 @@ \end{verbatim} } -% Does anyone have a better word to describe the phylosophy of spliting changes to patches? -You need to realize that the changes you have made should be well devided into +% Does anyone have a better word to describe the philosophy of splitting changes to patches? +You need to realize that the changes you have made should be well divided into several commits. Each of them has one and only one meaning. You could use git rebase -i to split, squash, remove, rewrite you comment. -- To view, visit https://review.coreboot.org/25571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I25dca2e231343cfdad61a638f0302726a6aa3f8b Gerrit-Change-Number: 25571 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: nb/intel/x4x: Change memory layout to improve MTRR
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21634 ) Change subject: nb/intel/x4x: Change memory layout to improve MTRR ...................................................................... Patch Set 18: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69782/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24071/ : SUCCESS -- To view, visit https://review.coreboot.org/21634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Gerrit-Change-Number: 21634 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 20:27:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: commonlib/storage: Make pci sdhci code compile in romstage
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25067 ) Change subject: commonlib/storage: Make pci sdhci code compile in romstage ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69776/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24065/ : SUCCESS -- To view, visit https://review.coreboot.org/25067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9438d0b707c6ffaa61db80bd1d385112bc91cfc Gerrit-Change-Number: 25067 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 09 Apr 2018 19:42:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: Configure PCIe for APL/GLK WiFi
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25532 ) Change subject: soc/intel/apollolake: Configure PCIe for APL/GLK WiFi ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69781/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24070/ : SUCCESS -- To view, visit https://review.coreboot.org/25532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5 Gerrit-Change-Number: 25532 Gerrit-PatchSet: 2 Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 09 Apr 2018 19:37:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]soc/intel/cannonlake: Enable early mmc CMD0, CMD1
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25515 ) Change subject: [WIP]soc/intel/cannonlake: Enable early mmc CMD0, CMD1 ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69779/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/24066/ : SUCCESS -- To view, visit https://review.coreboot.org/25515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I854cf5d323062fde1c07dd0816af127efebaa195 Gerrit-Change-Number: 25515 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Apr 2018 19:30:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit April 2018