coreboot-gerrit April 2018

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Change in coreboot[master]: nb/intel/i945: Use common SMM_TSEG code
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25595 ) Change subject: nb/intel/i945: Use common SMM_TSEG code ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69862/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24144/ : SUCCESS -- To view, visit https://review.coreboot.org/25595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Gerrit-Change-Number: 25595 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:21:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/i945: Use parallel MP init
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25600 ) Change subject: nb/intel/i945: Use parallel MP init ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69866/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24148/ : SUCCESS -- To view, visit https://review.coreboot.org/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:21:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/pineview: Use common code for SMM in TSEG
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25598 ) Change subject: nb/intel/pineview: Use common code for SMM in TSEG ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69865/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24147/ : SUCCESS -- To view, visit https://review.coreboot.org/25598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Gerrit-Change-Number: 25598 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:20:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Use common code for SMM in TSEG
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25597 ) Change subject: nb/intel/x4x: Use common code for SMM in TSEG ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69864/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24146/ : SUCCESS -- To view, visit https://review.coreboot.org/25597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Gerrit-Change-Number: 25597 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:20:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Put stage cache in TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25606 Change subject: nb/intel/x4x: Put stage cache in TSEG ...................................................................... nb/intel/x4x: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/Makefile.inc A src/northbridge/intel/x4x/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/25606/1 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 0e1a20f..bd06f08 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -30,6 +30,7 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex @@ -47,4 +48,13 @@ hex default 0xe0000000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 5c64ca7..10a6d71 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -27,4 +27,7 @@ ramstage-y += gma.c ramstage-y += northbridge.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/x4x/stage_cache.c b/src/northbridge/intel/x4x/stage_cache.c new file mode 100644 index 0000000..8ac3171 --- /dev/null +++ b/src/northbridge/intel/x4x/stage_cache.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include "x4x.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; +#ifdef __SIMPLE_DEVICE__ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), D0F0_ESMRAMC); +#else + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + D0F0_ESMRAMC); +#endif + const u32 tseg_size = decode_tseg_size(esmramc); + *base = (void *)((uintptr_t)cbmem_top() + tseg_size + - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE); +} -- To view, visit https://review.coreboot.org/25606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8 Gerrit-Change-Number: 25606 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/pineview: Put stage cache in TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25605 Change subject: nb/intel/pineview: Put stage cache in TSEG ...................................................................... nb/intel/pineview: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/Makefile.inc A src/northbridge/intel/pineview/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/25605/1 diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 9e5a1c1..5b5b20d 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -31,6 +31,7 @@ select INTEL_GMA_ACPI select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_NORTHBRIDGE_INIT string @@ -40,4 +41,13 @@ string default "8086,a001" +config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index a4c08c8..8e8b393 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -25,4 +25,7 @@ romstage-y += raminit.c romstage-y += early_init.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c new file mode 100644 index 0000000..bbe4fcd --- /dev/null +++ b/src/northbridge/intel/pineview/stage_cache.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include "pineview.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; +#ifdef __SIMPLE_DEVICE__ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), ESMRAMC); +#else + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + ESMRAMC); +#endif + const u32 tseg_size = decode_tseg_size(esmramc); + *base = (void *)((uintptr_t)cbmem_top() + tseg_size + - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE); +} -- To view, visit https://review.coreboot.org/25605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Gerrit-Change-Number: 25605 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25604 Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... nb/intel/gm45: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25604/1 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 34f23d4..51dbaef 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -31,6 +31,7 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config CBFS_SIZE hex @@ -48,4 +49,13 @@ hex default 0xf0000000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index fdf0012..c0e37dd 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -36,4 +36,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c new file mode 100644 index 0000000..126f4d8 --- /dev/null +++ b/src/northbridge/intel/gm45/stage_cache.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include "gm45.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; +#ifdef __SIMPLE_DEVICE__ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), D0F0_ESMRAMC); +#else + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + D0F0_ESMRAMC); +#endif + const u32 tseg_size = decode_tseg_size(esmramc); + *base = (void *)((uintptr_t)cbmem_top() + tseg_size + - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE); +} -- To view, visit https://review.coreboot.org/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/i945: Put stage cache in TSEG
by Arthur Heymans (Code Review) 10 Apr '18

10 Apr '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25603 Change subject: nb/intel/i945: Put stage cache in TSEG ...................................................................... nb/intel/i945: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/Makefile.inc A src/northbridge/intel/i945/stage_cache.c 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/25603/1 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 05e2d49..9b3777b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,6 +30,7 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select SMM_TSEG select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n @@ -89,4 +90,14 @@ On other boards the check always creates a false positive, effectively making it impossible to resume. +config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + + endif diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 0e4fcfc..0772212 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -29,4 +29,7 @@ smm-y += udelay.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + endif diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c new file mode 100644 index 0000000..e1e2ffb --- /dev/null +++ b/src/northbridge/intel/i945/stage_cache.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <stage_cache.h> +#include "i945.h" + +void stage_cache_external_region(void **base, size_t *size) +{ + /* + * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; +#ifdef __SIMPLE_DEVICE__ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), ESMRAMC); +#else + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + ESMRAMC); +#endif + const u32 tseg_size = decode_tseg_size(esmramc); + *base = (void *)((uintptr_t)cbmem_top() + tseg_size + - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE); +} -- To view, visit https://review.coreboot.org/25603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da Gerrit-Change-Number: 25603 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/i82801jx: Use common Intel SMM code
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25596 ) Change subject: sb/intel/i82801jx: Use common Intel SMM code ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69863/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24145/ : SUCCESS -- To view, visit https://review.coreboot.org/25596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3 Gerrit-Change-Number: 25596 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:15:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801gx: Use common Intel SMM code
by build bot (Jenkins) (Code Review) 10 Apr '18

10 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25594 ) Change subject: sb/intel/i82801gx: Use common Intel SMM code ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/69860/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/24142/ : SUCCESS -- To view, visit https://review.coreboot.org/25594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If7016a3b98fc5f14c287ce800325084f9dc602a0 Gerrit-Change-Number: 25594 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 14:13:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit April 2018