coreboot-gerrit April 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by build bot (Jenkins) (Code Review) 11 Apr '18

11 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25604 ) Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... Patch Set 4: No Builds Executed -- To view, visit https://review.coreboot.org/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 15:27:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by Arthur Heymans (Code Review) 11 Apr '18

11 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25604 to look at the new patch set (#5). Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... nb/intel/gm45: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25604/5 -- To view, visit https://review.coreboot.org/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/gm45: Use common code for SMM in TSEG
by build bot (Jenkins) (Code Review) 11 Apr '18

11 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23419 ) Change subject: nb/intel/gm45: Use common code for SMM in TSEG ...................................................................... Patch Set 20: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24176/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69894/ : SUCCESS -- To view, visit https://review.coreboot.org/23419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic80c65ea42fcf554ea5695772e8828d2f3b00b98 Gerrit-Change-Number: 23419 Gerrit-PatchSet: 20 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 15:26:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl1: Fix for using IDT PMIC
by Mario Scheithauer (Code Review) 11 Apr '18

11 Apr '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25585 to look at the new patch set (#2). Change subject: siemens/mc_apl1: Fix for using IDT PMIC ...................................................................... siemens/mc_apl1: Fix for using IDT PMIC Due to an accuracy issue on IMON in the IDT PMIC, the reported system power consumption was higher than the actual consumption. To prevent this problem, a logic must be implement in mainboard_init(). This logic consists of slope and offset as constants for Vcc and Vnn, which needs to be programmed by coreboot. This fix compensates for the accuracy issue. Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c 1 file changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/25585/2 -- To view, visit https://review.coreboot.org/25585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25 Gerrit-Change-Number: 25585 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by build bot (Jenkins) (Code Review) 11 Apr '18

11 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25604 ) Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... Patch Set 3: No Builds Executed -- To view, visit https://review.coreboot.org/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 15:26:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/gm45: Put stage cache in TSEG
by Arthur Heymans (Code Review) 11 Apr '18

11 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25604 to look at the new patch set (#4). Change subject: nb/intel/gm45: Put stage cache in TSEG ...................................................................... nb/intel/gm45: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Untested. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25604/4 -- To view, visit https://review.coreboot.org/25604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Gerrit-Change-Number: 25604 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/i945: Add a common function to compute TSEG size
by build bot (Jenkins) (Code Review) 11 Apr '18

11 Apr '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23448 ) Change subject: nb/intel/i945: Add a common function to compute TSEG size ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/24177/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69895/ : SUCCESS -- To view, visit https://review.coreboot.org/23448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Gerrit-Change-Number: 23448 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 10 Apr 2018 15:22:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/pineview: Use common code for SMM in TSEG
by Arthur Heymans (Code Review) 11 Apr '18

11 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25598 to look at the new patch set (#3). Change subject: nb/intel/pineview: Use common code for SMM in TSEG ...................................................................... nb/intel/pineview: Use common code for SMM in TSEG This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Untested. Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/pineview/ram_calc.c 4 files changed, 63 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25598/3 -- To view, visit https://review.coreboot.org/25598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Gerrit-Change-Number: 25598 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x: Use common code for SMM in TSEG
by Arthur Heymans (Code Review) 11 Apr '18

11 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25597 to look at the new patch set (#3). Change subject: nb/intel/x4x: Use common code for SMM in TSEG ...................................................................... nb/intel/x4x: Use common code for SMM in TSEG This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Untested Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smmrelocate.S M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/x4x.h M src/southbridge/intel/i82801jx/Makefile.inc D src/southbridge/intel/i82801jx/smi.c 7 files changed, 67 insertions(+), 208 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/25597/3 -- To view, visit https://review.coreboot.org/25597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Gerrit-Change-Number: 25597 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/i945: Use common SMM_TSEG code
by Arthur Heymans (Code Review) 11 Apr '18

11 Apr '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/25595 to look at the new patch set (#3). Change subject: nb/intel/i945: Use common SMM_TSEG code ...................................................................... nb/intel/i945: Use common SMM_TSEG code Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Untested. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/model_f4x/Makefile.inc M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/southbridge/intel/i82801gx/Makefile.inc 13 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25595/3 -- To view, visit https://review.coreboot.org/25595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Gerrit-Change-Number: 25595 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit April 2018