coreboot-gerrit March 2018

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Change in coreboot[master]: mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUD
by Duncan Laurie (Code Review) 26 Mar '18

26 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25368 Change subject: mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUD ...................................................................... mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUD Add an SPD for this particular Hynix memory type to the poppy board so it can be used by poppy variants. BUG=b:75454415 Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/25368/1 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex new file mode 100644 index 0000000..24c032b --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 47 41 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/25368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be Gerrit-Change-Number: 25368 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Add NHLT config for max98373 codec
by Duncan Laurie (Code Review) 26 Mar '18

26 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25367 Change subject: soc/intel/skylake: Add NHLT config for max98373 codec ...................................................................... soc/intel/skylake: Add NHLT config for max98373 codec Add the NHLT configuration for the max98373 codec to skylake, taken directly from cannonlake. This will allow skylake/kabylake boards to use this codec. Change-Id: Ifb6bf2d31fda25b18d9b1ce2bb721255335d55e4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/nhlt/Makefile.inc A src/soc/intel/skylake/nhlt/max98373.c 4 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/25367/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index aac4a8f..f76cf72 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -253,6 +253,12 @@ help Include DSP firmware settings for max98357 amplifier. +config NHLT_MAX98373 + bool + default n + help + Include DSP firmware settings for max98373 amplifier. + config NHLT_SSM4567 bool default n diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 1af27e8..a25e5ac 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -61,6 +61,12 @@ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); /* + * Add max98373 amplifier in stereo configuration on provided SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink); + +/* * Add rt5514 DSP on provided SSP link. Return 0 on success, < 0 on error. */ int nhlt_soc_add_rt5514(struct nhlt *nhlt, int hwlink, int num_channels); diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 9c9b4c8..5c8bd80 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c +ramstage-y += max98373.c ramstage-y += ssm4567.c ramstage-y += rt5514.c ramstage-y += rt5663.c @@ -20,6 +21,8 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin +MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin +MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin RT5514_CAPTURE = rt5514-capture-4ch-48khz-16b.bin @@ -52,6 +55,14 @@ $(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) $(MAX98357_RENDER)-type := raw +cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_16B) +$(MAX98373_RENDER_16B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_16B) +$(MAX98373_RENDER_16B)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_24B) +$(MAX98373_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_24B) +$(MAX98373_RENDER_24B)-type := raw + cbfs-files-$(CONFIG_NHLT_SSM4567) += $(SSM4567_RENDER) $(SSM4567_RENDER)-file := $(NHLT_BLOB_PATH)/$(SSM4567_RENDER) $(SSM4567_RENDER)-type := raw diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c new file mode 100644 index 0000000..6d357f6 --- /dev/null +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +static const struct nhlt_format_config max98373_render_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98373-render-2ch-48khz-24b.bin", + }, + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98373-render-2ch-48khz-16b.bin", + } +}; + +static const struct nhlt_format_config max98373_capture_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98373-render-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98373_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98373_render_formats, + .num_formats = ARRAY_SIZE(max98373_render_formats), + }, + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98373_capture_formats, + .num_formats = ARRAY_SIZE(max98373_capture_formats), + }, +}; + +int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98373_descriptors, + ARRAY_SIZE(max98373_descriptors)); +} -- To view, visit https://review.coreboot.org/25367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifb6bf2d31fda25b18d9b1ce2bb721255335d55e4 Gerrit-Change-Number: 25367 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled
by Duncan Laurie (Code Review) 26 Mar '18

26 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25366 Change subject: soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled ...................................................................... soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb. Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h 3 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/25366/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dab6622..fc73210 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,6 +70,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index b2689b0..590bb45 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -180,7 +181,7 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; - const struct device *dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; /* Parse device tree and enable/disable devices */ @@ -262,7 +263,11 @@ } } - params->XdciEnable = config->XdciEnable; + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 90956c3..2362c42 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -124,7 +124,6 @@ /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; - uint8_t XdciEnable; uint8_t SsicPortEnable; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; -- To view, visit https://review.coreboot.org/25366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1 Gerrit-Change-Number: 25366 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled
by Duncan Laurie (Code Review) 26 Mar '18

26 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25364 Change subject: soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled ...................................................................... soc/intel/apollolake: Limit xDCI feature when VBOOT is enabled Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. Change-Id: I5aea15511c52d1191babf551feb237f4144683e4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/xdci.c 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/25364/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cac2f11..1dd6daf 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -30,6 +30,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/p2sb.h> #include <intelblocks/msr.h> +#include <intelblocks/xdci.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -585,6 +586,12 @@ glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_XDCI); + if (!xdci_can_enable()) + dev->enabled = 0; + silconfig->UsbOtg = dev->enabled; } struct chip_operations soc_intel_apollolake_ops = { diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 4c3047c..07207b3 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -54,7 +54,7 @@ * enabled. If it's disabled assume the switch was already done * in FSP. */ - if (!dev->enabled || !xdci_dev->enabled) + if (!dev->enabled || !xdci_dev->enabled || !xdci_can_enable()) return; printk(BIOS_INFO, "Putting port 0 into host mode.\n"); -- To view, visit https://review.coreboot.org/25364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5aea15511c52d1191babf551feb237f4144683e4 Gerrit-Change-Number: 25364 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
by Duncan Laurie (Code Review) 26 Mar '18

26 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25365 Change subject: soc/intel/skylake: Limit xDCI feature when VBOOT is enabled ...................................................................... soc/intel/skylake: Limit xDCI feature when VBOOT is enabled Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/chell/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 15 files changed, 16 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25365/1 diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index f8c3054..2f07753 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -36,7 +36,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 2e62f41..f24d5c9 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -32,7 +32,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a9646ec..9d120ea 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -67,7 +67,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 0dff3d9..94d9e53 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -36,7 +36,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 074e8a2..032c426 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 0b3387e..a04dd95 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6946b38..8a94682 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 65955eb..2688d58 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7903ddc..6da73dc 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -170,7 +170,6 @@ # USB related register "SsicPortEnable" = "1" - register "XdciEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 1fc19a5..b7fff8a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -41,7 +41,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 647f054..fbc6942 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -41,7 +41,6 @@ register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index aac4a8f..f3719a5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,6 +84,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_GFX_OPREGION select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f60c08d..0c1dfa6 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <soc/acpi.h> #include <soc/interrupt.h> #include <soc/irq.h> @@ -78,7 +79,7 @@ /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; int i; @@ -140,7 +141,6 @@ params->EnableAzalia = config->EnableAzalia; params->IoBufferOwnership = config->IoBufferOwnership; params->DspEnable = config->DspEnable; - params->XdciEnable = config->XdciEnable; params->Device4Enable = config->Device4Enable; params->EnableSata = config->EnableSata; params->SataMode = config->SataMode; @@ -196,6 +196,12 @@ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + params->SendVrMbxCmd = config->SendVrMbxCmd; /* Acoustic Noise Mitigation */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b77f6dc..dc79869 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -237,7 +237,6 @@ /* USB related */ struct usb2_port_config usb2_ports[16]; struct usb3_port_config usb3_ports[10]; - u8 XdciEnable; u8 SsicPortEnable; /* SMBus */ diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3bc66b2..b4fed26 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -26,6 +26,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> @@ -221,7 +222,6 @@ params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; - params->XdciEnable = config->XdciEnable; params->Device4Enable = config->Device4Enable; params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; @@ -284,6 +284,12 @@ dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + /* * Send VR specific mailbox commands: * 000b - no VR specific command sent -- To view, visit https://review.coreboot.org/25365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic3c84beac87452f17490de32082030880834501d Gerrit-Change-Number: 25365 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/skylake: Do a heci_reset before reading ME firmware version
by build bot (Jenkins) (Code Review) 26 Mar '18

26 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25362 ) Change subject: soc/intel/skylake: Do a heci_reset before reading ME firmware version ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/69036/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/23393/ : SUCCESS -- To view, visit https://review.coreboot.org/25362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6 Gerrit-Change-Number: 25362 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Mar 2018 05:36:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/skylake: Do a heci_reset before reading ME firmware version
by Furquan Shaikh (Code Review) 26 Mar '18

26 Mar '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/25362 Change subject: soc/intel/skylake: Do a heci_reset before reading ME firmware version ...................................................................... soc/intel/skylake: Do a heci_reset before reading ME firmware version This change adds a call to heci_reset before attempting to read ME firmware version. This is important to ensure that both ME and BIOS are in sync. BUG=b:76167737 BRANCH=poppy TEST=Verfied that ME firmware version read does not fail on first boot after power failure (i.e. removing battery and AC power). Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/me.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25362/1 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 67d7bc0..9a721bc 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -254,6 +254,12 @@ (hfs.fields.operation_mode != ME_HFS_MODE_NORMAL)) goto failed; + /* + * It is important to do a heci_reset to ensure BIOS and ME are in sync + * before reading firmware version. + */ + heci_reset(); + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, HECI_MKHI_ADD)) goto failed; -- To view, visit https://review.coreboot.org/25362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6 Gerrit-Change-Number: 25362 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: util/intelvbttool: Rewrite tool
by build bot (Jenkins) (Code Review) 25 Mar '18

25 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18902 ) Change subject: util/intelvbttool: Rewrite tool ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23392/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69035/ : SUCCESS -- To view, visit https://review.coreboot.org/18902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76 Gerrit-Change-Number: 18902 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Mar 2018 16:11:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/*/devicetree: Add support for WWAN detection
by build bot (Jenkins) (Code Review) 25 Mar '18

25 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20984 ) Change subject: mb/lenovo/*/devicetree: Add support for WWAN detection ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23390/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69033/ : SUCCESS -- To view, visit https://review.coreboot.org/20984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie96b2593971d49703eb747ab19f512be890d9c12 Gerrit-Change-Number: 20984 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Mar 2018 15:44:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Makefile.inc: Update build.h on git change
by build bot (Jenkins) (Code Review) 25 Mar '18

25 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25348 ) Change subject: Makefile.inc: Update build.h on git change ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23391/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69034/ : SUCCESS -- To view, visit https://review.coreboot.org/25348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iddafcf8644ce4db7940a327530e5c50fd054545a Gerrit-Change-Number: 25348 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Mar 2018 15:44:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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