coreboot-gerrit March 2018

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Change in coreboot[master]: Makefile.inc: Update build.h on git change
by Patrick Rudolph (Code Review) 25 Mar '18

25 Mar '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/25348 Change subject: Makefile.inc: Update build.h on git change ...................................................................... Makefile.inc: Update build.h on git change Update the coreboot version if something in .git changed, too. Allows to gather the correct git sha1 using dmidecode -t0. Tested on Lenovo T430. Change-Id: Iddafcf8644ce4db7940a327530e5c50fd054545a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/25348/1 diff --git a/Makefile.inc b/Makefile.inc index b11f6e2..73058d3 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -456,7 +456,7 @@ ####################################################################### # generate build support files -$(obj)/build.h: .xcompile +$(obj)/build.h: .xcompile .git/**/* @printf " GEN build.h\n" rm -f $(obj)/build.h util/genbuild_h/genbuild_h.sh > $(obj)/build.ht -- To view, visit https://review.coreboot.org/25348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iddafcf8644ce4db7940a327530e5c50fd054545a Gerrit-Change-Number: 25348 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/peg: Add PEG driver stub
by build bot (Jenkins) (Code Review) 25 Mar '18

25 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22337 ) Change subject: nb/intel/sandybridge/peg: Add PEG driver stub ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/23389/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/69032/ : SUCCESS -- To view, visit https://review.coreboot.org/22337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Gerrit-Change-Number: 22337 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Mar 2018 14:57:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [RFC]drivers/intel/gma: Add common devicetree structure
by Patrick Rudolph (Code Review) 25 Mar '18

25 Mar '18

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/23502 ) Change subject: [RFC]drivers/intel/gma: Add common devicetree structure ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/23502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I29c5090a21537f823d14bda2b1d5f03dd8d58c1c Gerrit-Change-Number: 23502 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Limit xDCI feature when VBOOT is enabled
by build bot (Jenkins) (Code Review) 25 Mar '18

25 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25347 ) Change subject: soc/intel: Limit xDCI feature when VBOOT is enabled ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23388/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69031/ : SUCCESS -- To view, visit https://review.coreboot.org/25347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b Gerrit-Change-Number: 25347 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 25 Mar 2018 04:24:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Limit xDCI feature when VBOOT is enabled
by Duncan Laurie (Code Review) 25 Mar '18

25 Mar '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/25347 Change subject: soc/intel: Limit xDCI feature when VBOOT is enabled ...................................................................... soc/intel: Limit xDCI feature when VBOOT is enabled When CONFIG_VBOOT is enabled then the xDCI controller should only be enabled if the system is in developer mode. This prevents a system in normal/verified mode from being used as a USB peripheral device which could potentially be used to access user data. Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/include/intelblocks/xdci.h M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip_fsp20.c 8 files changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25347/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cac2f11..d93985e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -30,6 +30,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/p2sb.h> #include <intelblocks/msr.h> +#include <intelblocks/xdci.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -585,6 +586,10 @@ glk_fsp_silicon_init_params_cb(cfg, silconfig); else apl_fsp_silicon_init_params_cb(cfg, silconfig); + + /* Disable xDCI device if it should not be enabled */ + dev = dev_find_slot(0, PCH_DEVFN_XDCI); + silconfig->UsbOtg = xdci_can_enable() ? dev->enabled : 0; } struct chip_operations soc_intel_apollolake_ops = { diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 4c3047c..07207b3 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -54,7 +54,7 @@ * enabled. If it's disabled assume the switch was already done * in FSP. */ - if (!dev->enabled || !xdci_dev->enabled) + if (!dev->enabled || !xdci_dev->enabled || !xdci_can_enable()) return; printk(BIOS_INFO, "Putting port 0 into host mode.\n"); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dab6622..fc73210 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,6 +70,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index b2689b0..c64de71 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -262,7 +263,7 @@ } } - params->XdciEnable = config->XdciEnable; + params->XdciEnable = xdci_can_enable() ? config->XdciEnable : 0; /* PCI Express */ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { diff --git a/src/soc/intel/common/block/include/intelblocks/xdci.h b/src/soc/intel/common/block/include/intelblocks/xdci.h index fa25513..1158056 100644 --- a/src/soc/intel/common/block/include/intelblocks/xdci.h +++ b/src/soc/intel/common/block/include/intelblocks/xdci.h @@ -17,5 +17,6 @@ #define SOC_INTEL_COMMON_BLOCK_XDCI_H void soc_xdci_init(struct device *dev); +int xdci_can_enable(void); #endif /* SOC_INTEL_COMMON_BLOCK_XDCI_H */ diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 10e6f0d..07093df 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -19,9 +19,19 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/xdci.h> +#include <security/vboot/vboot_common.h> __attribute__((weak)) void soc_xdci_init(struct device *dev) { /* no-op */ } +/* Only allow xDCI controller in developer mode if VBOOT is enabled */ +int xdci_can_enable(void) +{ + if (IS_ENABLED(CONFIG_VBOOT)) + return vboot_developer_mode_enabled() ? 1 : 0; + else + return 1; +} + static struct device_operations usb_xdci_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index aac4a8f..f3719a5 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,6 +84,7 @@ select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_GFX_OPREGION select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3bc66b2..3b1407b 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -26,6 +26,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> @@ -221,7 +222,7 @@ params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; - params->XdciEnable = config->XdciEnable; + params->XdciEnable = xdci_can_enable() ? config->XdciEnable : 0; params->Device4Enable = config->Device4Enable; params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; -- To view, visit https://review.coreboot.org/25347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b Gerrit-Change-Number: 25347 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: vboot: Update to most recent GBB flag usage
by build bot (Jenkins) (Code Review) 24 Mar '18

24 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25346 ) Change subject: vboot: Update to most recent GBB flag usage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23387/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69030/ : SUCCESS -- To view, visit https://review.coreboot.org/25346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I585d662d7de34b4964d028e3d06b4df5665fbe9e Gerrit-Change-Number: 25346 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Mar 2018 04:16:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: vboot: Update to most recent GBB flag usage
by Julius Werner (Code Review) 24 Mar '18

24 Mar '18

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/25346 to review the following change. Change subject: vboot: Update to most recent GBB flag usage ...................................................................... vboot: Update to most recent GBB flag usage This patch changes the GBB flag configuration to the latest usage in upstream vboot (as of https://chromium-review.googlesource.com/976660). Change-Id: I585d662d7de34b4964d028e3d06b4df5665fbe9e Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25346/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e2a3f20..8d8e120 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -303,8 +303,12 @@ bool "Allow fastboot even if dev_boot_fastboot_full_cap=0" default n -config GBB_FLAG_ENABLE_SERIAL - bool "Tell vboot to enable serial console" +config GBB_FLAG_FORCE_MANUAL_RECOVERY + bool "Always assume manual recovery in recovery mode" + default n + +config GBB_FLAG_DISABLE_FWMP + bool "Disable Firmware Management Parameters (FWMP)" default n endmenu # GBB diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 75ecff3..53462d9 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -182,7 +182,8 @@ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC),0x800) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_LID_SHUTDOWN),0x1000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP),0x2000) \ - $(call bool-to-mask,$(CONFIG_GBB_FLAG_ENABLE_SERIAL),0x4000) \ + $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ + $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ ) ifneq ($(CONFIG_GBB_BMPFV_FILE),) -- To view, visit https://review.coreboot.org/25346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I585d662d7de34b4964d028e3d06b4df5665fbe9e Gerrit-Change-Number: 25346 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent and enable S0ix
by build bot (Jenkins) (Code Review) 23 Mar '18

23 Mar '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25312 ) Change subject: mainboard/google/meowth: Disable debug consent and enable S0ix ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/23386/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/69029/ : SUCCESS -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 3 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Mar 2018 23:26:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent and enable S0ix
by Vaibhav Shankar (Code Review) 23 Mar '18

23 Mar '18

Vaibhav Shankar has posted comments on this change. ( https://review.coreboot.org/25312 ) Change subject: mainboard/google/meowth: Disable debug consent and enable S0ix ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/25312/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/25312/2//COMMIT_MSG@13 PS2, Line 13: 76163091 > that should be b:76163091 Done -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 2 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Mar 2018 23:18:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/meowth: Disable debug consent and enable S0ix
by Vaibhav Shankar (Code Review) 23 Mar '18

23 Mar '18

Hello Nick Vaccaro, Bora Guvendik, Lijian Zhao, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/25312 to look at the new patch set (#3). Change subject: mainboard/google/meowth: Disable debug consent and enable S0ix ...................................................................... mainboard/google/meowth: Disable debug consent and enable S0ix This patch disables debug consent in the devicetree. When debug conset is set to DBC by default, it prevents some clocks from turning off during S0ix. This blocks S0ix entry. This patch also enables S0ix from the devicetree. b:76163091 TEST=enter S0ix and check if slp_s0 is asserted Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- M src/mainboard/google/zoombini/variants/meowth/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/25312/3 -- To view, visit https://review.coreboot.org/25312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Gerrit-Change-Number: 25312 Gerrit-PatchSet: 3 Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit March 2018