coreboot-gerrit February 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Refactor northbridge RAM resource allocator
by Marc Jones (Code Review) 19 Feb '18

19 Feb '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/23819 Change subject: soc/amd/stoneyridge: Refactor northbridge RAM resource allocator ...................................................................... soc/amd/stoneyridge: Refactor northbridge RAM resource allocator The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 50 insertions(+), 126 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23819/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 2449077..98f7ea1 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -40,35 +40,6 @@ #include <stdlib.h> #include <string.h> -typedef struct dram_base_mask { - u32 base; /* [47:27] at [28:8] */ - u32 mask; /* [47:27] at [28:8] and enable at bit 0 */ -} dram_base_mask_t; - -static dram_base_mask_t get_dram_base_mask(void) -{ - device_t dev = dev_find_slot(0, ADDR_DEVFN); - dram_base_mask_t d; - u32 temp; - - /* [39:24] at [31:16] */ - temp = pci_read_config32(dev, 0x44); - - /* mask out DramMask [26:24] too */ - d.mask = ((temp & 0xfff80000) >> (8 + 3)); - - /* [47:40] at [7:0] */ - temp = pci_read_config32(dev, 0x144) & 0xff; - d.mask |= temp << 21; - - temp = pci_read_config32(dev, 0x40); - d.mask |= (temp & 1); /* enable bit */ - d.base = ((temp & 0xfff80000) >> (8 + 3)); - temp = pci_read_config32(dev, 0x140) & 0xff; - d.base |= temp << 21; - return d; -} - static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { @@ -433,109 +404,62 @@ void domain_set_resources(device_t dev) { - unsigned long mmio_basek; - u32 pci_tolm; - u32 hole; - int idx; - struct bus *link; - void *tseg_base; - size_t tseg_size; + uint64_t uma_base = get_uma_base(); + uint32_t uma_size = get_uma_size(); + uint32_t mem_useable = (uint32_t)cbmem_top(); + msr_t tom = rdmsr(TOP_MEM); + msr_t high_tom = rdmsr(TOP_MEM2); + uint64_t high_mem_useable = 0; + int idx = 0x10; - pci_tolm = 0xffffffffUL; - for (link = dev->link_list ; link ; link = link->next) - pci_tolm = find_pci_tolm(link); + /* 0x0 - 0x9ffff */ + ram_resource(dev, idx, 0, 0xa0000 / KiB); + idx += 0x10; - /* Start with alignment supportable in variable MTRR */ - mmio_basek = ALIGN_DOWN(pci_tolm, 4 * KiB) / KiB; - - /* - * AGESA may have programmed the memory hole and rounded down to a - * 128MB boundary. If we find it's valid, adjust mmio_basek downward - * to the hole bottom. D18F1xF0[DramHoleBase] is granular to 16MB. - */ - hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), D18F1_DRAM_HOLE); - if (hole & DRAM_HOLE_VALID) - mmio_basek = min(mmio_basek, ALIGN_DOWN(hole, 16 * MiB) / KiB); - - idx = 0x10; - dram_base_mask_t d; - resource_t basek, limitk, sizek; /* 4 1T */ - - d = get_dram_base_mask(); - - if ((d.mask & 1)) { /* if enabled... */ - /* could overflow, we may lose 6 bit here */ - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; - limitk = ((resource_t)(((d.mask & ~1) + 0x000ff) - & 0x1fffff00)) << 9; - - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) + - (16 * 16)))) { - ram_resource(dev, idx, basek, - ((8 * 64) + (8 * 16)) - basek); - idx += 0x10; - basek = (8 * 64) + (16 * 16); - sizek = limitk - ((8 * 64) + (16 * 16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, idx, basek, - pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4 * 1024 * 1024) { - sizek = 0; - } else { - uint64_t topmem2 = bsp_topmem2(); - basek = 4 * 1024 * 1024; - sizek = topmem2 / 1024 - basek; - } - } - - ram_resource(dev, idx, basek, sizek); - printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx," - " limitk=%08llx\n", mmio_basek, basek, limitk); - } - - /* UMA is not set up yet, but infer the base & size to make cacheable */ - uint32_t uma_base = restore_top_of_low_cacheable(); - if (uma_base != bsp_topmem()) { - uint32_t uma_size = bsp_topmem() - uma_base; - printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", - __func__, uma_size, uma_base); - reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB); - } - - for (link = dev->link_list ; link ; link = link->next) - if (link->children) - assign_resources(link); - - /* - * Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xfffff: RAM - */ + /* 0xa0000 - 0xbffff: legacy VGA */ mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB); + + /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB); - /* Reserve TSEG */ - smm_region_info(&tseg_base, &tseg_size); + /* + * 0x100000 - lower top useable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_resource(dev, idx, 0x100000 / KiB, (mem_useable - 0x100000) / KiB); idx += 0x10; - reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB, - tseg_size/KiB); + + /* Lower top useable RAM - Lower top RAM (pci mmio hole) */ + reserved_ram_resource(dev, idx, mem_useable / KiB, + (tom.lo - mem_useable) / KiB); + idx += 0x10; + + /* If there is memory above 4GB */ + if (high_tom.hi) { + /* 4GB - > high top useable */ + if (uma_base >= (4ull * GiB)) + high_mem_useable = uma_base; + else + high_mem_useable = ((uint64_t)high_tom.lo | + ((uint64_t)high_tom.hi << 32)); + + ram_resource(dev, idx, (4ull * GiB) / KiB, + ((high_mem_useable - (4ull * GiB)) / KiB)); + idx += 0x10; + + /* High top useable RAM - high top RAM*/ + if (uma_base >= (4ull * GiB)) { + reserved_ram_resource(dev, 7, uma_base / KiB, + uma_size / KiB); + idx += 0x10; + } + + /* Sanity check that something isn't misaligned on the end */ + assert((uma_base + uma_size) == ((uint64_t)high_tom.lo | + ((uint64_t)high_tom.hi << 32))); + } + + assign_resources(dev->link_list); } /********************************************************************* -- To view, visit https://review.coreboot.org/23819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Gerrit-Change-Number: 23819 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: soc/amd/common: Save the UMA settings from AGESA
by Marc Jones (Code Review) 19 Feb '18

19 Feb '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/23818 Change subject: soc/amd/common: Save the UMA settings from AGESA ...................................................................... soc/amd/common: Save the UMA settings from AGESA Save the UMA base and size settings returned by AGESA in amdinitpost(); Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M 3rdparty/blobs M src/soc/amd/common/block/pi/agesawrapper.c 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23818/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 19dea8d..a5efee5 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 19dea8d171544f01f12ee6b78af0cc356ab994aa +Subproject commit a5efee5fdea55f398decc9cabebce3744bbd8147 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index dca7222..cfa3760 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -26,6 +26,7 @@ #include <amdblocks/s3_resume.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -207,12 +208,16 @@ * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ uintptr_t top; - if (PostParams->MemConfig.UmaBase) + if (PostParams->MemConfig.UmaBase && + (PostParams->MemConfig.UmaBase < ((4ull * GiB) >> 16))) top = PostParams->MemConfig.UmaBase << 16; else top = PostParams->MemConfig.Sub4GCacheTop; backup_top_of_low_cacheable(top); + save_uma_size(PostParams->MemConfig.UmaSize * 64 * KiB); + save_uma_base((u64)PostParams->MemConfig.UmaBase * 64 * KiB); + print_init_post_settings(PostParams); if (status != AGESA_SUCCESS) -- To view, visit https://review.coreboot.org/23818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Gerrit-Change-Number: 23818 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add UMA save function
by Marc Jones (Code Review) 19 Feb '18

19 Feb '18

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/23817 Change subject: soc/amd/stoneyridge: Add UMA save function ...................................................................... soc/amd/stoneyridge: Add UMA save function Save the UMA values from AGESA to use in resource allocation in ramstage. Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 3 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23817/1 diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 2319b88..354a2db 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -68,5 +68,7 @@ /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xfa /* 8 bytes */ #endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index df78608..df1d755 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -340,6 +340,38 @@ uint32_t xhci_pm_read32(uint8_t reg); void bootblock_fch_early_init(void); /** + * @brief Save the UMA bize returned by AGESA + * + * @param size = in bytes + * + * @return none + */ +void save_uma_size(uint32_t size); +/** + * @brief Save the UMA base address returned by AGESA + * + * @param base = 64bit base address + * + * @return none + */ +void save_uma_base(uint64_t base); +/** + * @brief Get the saved UMA size + * + * @param none + * + * @return size in bytes + */ +int32_t get_uma_size(void); +/** + * @brief Get the saved UMA base + * + * @param none + * + * @return 64bit base address + */ +int64_t get_uma_base(void); +/** * @brief program a particular set of GPIO * * @param gpio_ptr = pointer to array of gpio configurations diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index a98a334..eda3fc8 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -164,3 +164,27 @@ { return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); } + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +int32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +int64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} -- To view, visit https://review.coreboot.org/23817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e Gerrit-Change-Number: 23817 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: Fizz: Check HDMI HPD and DisplayPort HPD
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23816 ) Change subject: Fizz: Check HDMI HPD and DisplayPort HPD ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67692/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22196/ : SUCCESS -- To view, visit https://review.coreboot.org/23816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Gerrit-Change-Number: 23816 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 17:55:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Fizz: Check HDMI HPD and DisplayPort HPD
by Daisuke Nojiri (Code Review) 19 Feb '18

19 Feb '18

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/23816 Change subject: Fizz: Check HDMI HPD and DisplayPort HPD ...................................................................... Fizz: Check HDMI HPD and DisplayPort HPD Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if HDMI monitor is connected, no wait is needed. If only HDMI monitor is connected, the API always loops until stopwatch expires. This patch will make google_chromeec_wait_for_displayport first check HDMI HPD. If it's asserted, it returns immediately. If not, it loops until DP HPD is asserted. This patch also extends the wait time to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not imeediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/mainboard/google/fizz/ramstage.c 3 files changed, 54 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/23816/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index c902c3f..e03a96f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -986,25 +986,32 @@ return 0; } -const static long wait_for_display_timeout_ms = 2000; #define USB_SID_DISPLAYPORT 0xff01 -void google_chromeec_wait_for_display(void) +/** + * Wait for DisplayPort to be ready + * + * @param timeout Wait aborts after <timeout> ms. + * @return 1: Success or 0: Timeout. + */ +int google_chromeec_wait_for_displayport(long timeout) { struct stopwatch sw; - printk(BIOS_INFO, "Waiting for display\n"); - stopwatch_init_msecs_expire(&sw, wait_for_display_timeout_ms); + printk(BIOS_INFO, "Waiting for DisplayPort\n"); + stopwatch_init_msecs_expire(&sw, timeout); while (google_chromeec_pd_get_amode(USB_SID_DISPLAYPORT) != 1) { if (stopwatch_expired(&sw)) { printk(BIOS_WARNING, - "Display not ready after %ldms. Abort.\n", - wait_for_display_timeout_ms); - return; + "DisplayPort not ready after %ldms. Abort.\n", + timeout); + return 0; } mdelay(200); } - printk(BIOS_INFO, "Display ready after %lu ms\n", + printk(BIOS_INFO, "DisplayPort ready after %lu ms\n", stopwatch_duration_msecs(&sw)); + + return 1; } diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 1ff07b7..24c8922 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -37,7 +37,7 @@ int google_ec_running_ro(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); -void google_chromeec_wait_for_display(void); +int google_chromeec_wait_for_displayport(long timeout); /* Device events */ uint64_t google_chromeec_get_device_enabled_events(void); diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c index e5215f8..f7520fa 100644 --- a/src/mainboard/google/fizz/ramstage.c +++ b/src/mainboard/google/fizz/ramstage.c @@ -14,15 +14,51 @@ */ #include <bootmode.h> +#include <console/console.h> +#include <delay.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <mainboard/google/fizz/gpio.h> +#include <soc/gpio.h> #include <soc/ramstage.h> +#include <timer.h> #include "gpio.h" +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +const static long display_timeout_ms = 3000; + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + gpio_input(gpio); + + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - if (display_init_required()) + gpio_input(GPIO_HDMI_HPD); + if (display_init_required() && !gpio_get(GPIO_HDMI_HPD)) { /* This has to be done before FSP-S runs. */ - google_chromeec_wait_for_display(); + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } -- To view, visit https://review.coreboot.org/23816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Gerrit-Change-Number: 23816 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 32: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67691/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22195/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 32 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 17:26:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 31: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67690/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22194/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 31 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 17:11:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 30: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67689/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/22193/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 30 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 17:07:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Refactor TSS 1.2 and 2.0 implementation
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22374 ) Change subject: security/tpm: Refactor TSS 1.2 and 2.0 implementation ...................................................................... Patch Set 29: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/67688/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/22192/ : SUCCESS -- To view, visit https://review.coreboot.org/22374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97bbc7b7b025500b49c743b0c303543c33627c88 Gerrit-Change-Number: 22374 Gerrit-PatchSet: 29 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 16:44:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: driver/uart: Introduce a way for mainboard to override the baudrate
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23713 ) Change subject: driver/uart: Introduce a way for mainboard to override the baudrate ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67683/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/22187/ : SUCCESS -- To view, visit https://review.coreboot.org/23713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Gerrit-Change-Number: 23713 Gerrit-PatchSet: 3 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 15:48:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit February 2018