coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block/pcr: Add function for executing PCH SBI message
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23809 ) Change subject: soc/intel/common/block/pcr: Add function for executing PCH SBI message ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67704/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22208/ : SUCCESS -- To view, visit https://review.coreboot.org/23809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e49311564e20cedbfabaaceaf5f72c480e5ea26 Gerrit-Change-Number: 23809 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Tung Lun Loo <tung.lun.loo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 20 Feb 2018 06:57:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add provision to make CSME function disable in ...
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23824 ) Change subject: soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67707/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22211/ : SUCCESS -- To view, visit https://review.coreboot.org/23824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Gerrit-Change-Number: 23824 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 06:55:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add provision to make CSME function disable in ...
by Subrata Banik (Code Review) 20 Feb '18

20 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23824 Change subject: soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode ...................................................................... soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pcr_ids.h M src/soc/intel/cannonlake/smihandler.c 3 files changed, 92 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/23824/1 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index df4def2..37399a6 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -33,49 +33,12 @@ #include <soc/systemagent.h> #include <stdlib.h> -#define PSF_BASE_ADDRESS 0x300 -#define PCR_PSFX_T0_SHDW_PCIEN 0x1C -#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) - #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) #define MIPI_CLK (1 << 0) #define HDPLL_CLK (0 << 0) -static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) -{ - uint32_t reg32; - - reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); - pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); -} - -static void disable_sideband_access(void) -{ - device_t dev; - u8 reg8; - uint32_t mask; - - dev = PCH_DEV_P2SB; - - /* Remove the host accessing right to PSF register range. */ - /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */ - mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); - pch_configure_endpoints(dev, 5, mask); - - /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ - reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); - pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); -} - -static void pch_disable_heci(void) -{ - pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, - PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); - disable_sideband_access(); -} - static void pch_enable_isclk(void) { pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); @@ -89,20 +52,11 @@ if (!dev) return; - if (config->HeciEnabled && !config->pch_isclk) + if (!config->pch_isclk) return; - /* unhide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); - - if (config->HeciEnabled == 0) - pch_disable_heci(); - if (config->pch_isclk) pch_enable_isclk(); - - /* hide p2sb device */ - pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); } static void pch_finalize(void) diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index b77eab8..04ea147 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -25,6 +25,7 @@ #define PID_GPIOCOM0 0x6e #define PID_DMI 0x88 #define PID_PSTH 0x89 +#define PID_CSME0 0x90 #define PID_ISCLK 0xad #define PID_PSF1 0xba #define PID_PSF2 0xbb diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index f40e81d..dac57ac 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -15,16 +15,106 @@ * GNU General Public License for more details. */ +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/pcr.h> #include <intelblocks/smihandler.h> +#include <soc/p2sb.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> +#define CSME0_FBE 0xf +#define CSME0_BAR 0x0 +#define CSME0_FID 0xb0 + const struct smm_save_state_ops *get_smm_save_state_ops(void) { return &em64t101_smm_ops; } +static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask) +{ + uint32_t reg32; + + reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id)); + pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask); +} + +static void disable_sideband_access(device_t dev) +{ + u8 reg8; + uint32_t mask; + + /* Remove the host accessing right to PSF register range. */ + /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */ + mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26); + pch_configure_endpoints(dev, 5, mask); + + /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */ + reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2); + pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1)); +} + +static void pch_disable_heci(void) +{ + device_t dev = PCH_DEV_P2SB; + struct pcr_sbi_msg sbi_msg; + struct pcr_sbi_msg *msg = &sbi_msg; + uint32_t data32 = 0; + uint8_t response; + int status; + + /* unhide p2sb device */ + pci_write_config8(dev, PCH_P2SB_E0 + 1, 0); + + /* disable heci#1 */ + msg->pid = PID_CSME0; + msg->offset = 0; + msg->opcode = PCR_WRITE; + msg->is_posted = false; + msg->fast_byte_enable = CSME0_FBE; + msg->bar = CSME0_BAR; + msg->fid = CSME0_FID; + /* Bit 0: Set to make HECI#1 Function disable */ + data32 |= 0x1; + response = 0; + /* Send SBI command to make HECI#1 function disable */ + status = pcr_execute_sideband_msg (msg, &data32, &response); + + /* Ensure to Lock SBI interface after this command */ + disable_sideband_access(dev); + + /* hide p2sb device */ + pci_write_config8(dev, PCH_P2SB_E0 + 1, 1); +} + +/* + * Specific SOC SMI handler during ramstage finalize phase + * + * BIOS can't make CSME function disable as is due to POSTBOOT_SAI + * restriction in place from CNP chipset. Hence create SMI Handler to + * perform CSME function disabling logic during SMM mode. + */ +void smihandler_soc_at_finalize(void) +{ + const struct soc_intel_cannonlake_config *config; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return ; + } + + config = dev->chip_info; + + if (config->HeciEnabled == 0) + pch_disable_heci(); +} + void smihandler_soc_check_illegal_access(uint32_t tco_sts) { if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM) -- To view, visit https://review.coreboot.org/23824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Gerrit-Change-Number: 23824 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: device: Include devicetree in SMM stage
by Subrata Banik (Code Review) 20 Feb '18

20 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23823 Change subject: device: Include devicetree in SMM stage ...................................................................... device: Include devicetree in SMM stage Allow bootblock to get access to the entire static device tree as other stages can access independently. TEST=SMM code now can access devicetree.cb variables. Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M Makefile.inc M src/device/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/23823/1 diff --git a/Makefile.inc b/Makefile.inc index be658ef..b11f6e2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -550,6 +550,7 @@ verstage-y+=$(DEVICETREE_STATIC_C) bootblock-y+=$(DEVICETREE_STATIC_C) postcar-y+=$(DEVICETREE_STATIC_C) +smm-y+=$(DEVICETREE_STATIC_C) ####################################################################### # Clean up rules diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index a1d5920..af5e7a9 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -22,6 +22,7 @@ bootblock-y += device_simple.c postcar-y += device_simple.c +smm-y += device_simple.c verstage-y += device_simple.c romstage-y += device_simple.c romstage-$(CONFIG_PCI) += pci_early.c -- To view, visit https://review.coreboot.org/23823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Gerrit-Change-Number: 23823 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add UMA save function
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23817 ) Change subject: soc/amd/stoneyridge: Add UMA save function ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67701/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22205/ : SUCCESS -- To view, visit https://review.coreboot.org/23817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e Gerrit-Change-Number: 23817 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 00:57:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common: Save the UMA settings from AGESA
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23818 ) Change subject: soc/amd/common: Save the UMA settings from AGESA ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67703/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22207/ : SUCCESS -- To view, visit https://review.coreboot.org/23818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Gerrit-Change-Number: 23818 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 00:55:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Refactor northbridge resource allocator
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23819 ) Change subject: soc/amd/stoneyridge: Refactor northbridge resource allocator ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67702/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22206/ : SUCCESS -- To view, visit https://review.coreboot.org/23819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Gerrit-Change-Number: 23819 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 00:53:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/broadwell: Enable VT-d and X2APIC
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23820 ) Change subject: soc/intel/broadwell: Enable VT-d and X2APIC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67699/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22203/ : SUCCESS -- To view, visit https://review.coreboot.org/23820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Gerrit-Change-Number: 23820 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 23:56:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/broadwell: Generate ACPI DMAR table
by build bot (Jenkins) (Code Review) 19 Feb '18

19 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23821 ) Change subject: soc/intel/broadwell: Generate ACPI DMAR table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67700/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22204/ : SUCCESS -- To view, visit https://review.coreboot.org/23821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Gerrit-Change-Number: 23821 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Feb 2018 23:51:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/broadwell: Generate ACPI DMAR table
by Matt DeVillier (Code Review) 19 Feb '18

19 Feb '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23821 Change subject: soc/intel/broadwell: Generate ACPI DMAR table ...................................................................... soc/intel/broadwell: Generate ACPI DMAR table If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/chip.c M src/soc/intel/broadwell/include/soc/acpi.h 3 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23821/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index a23c8e2..6f89e43 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -37,6 +37,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> /* @@ -571,6 +572,56 @@ } } +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; + const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; + + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && + gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + + acpi_dmar_drhd_fixup(tmp, current); + } + + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} + unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 8176c8e..a0ffd5a 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> @@ -30,6 +31,9 @@ .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, .ops_pci_bus = &pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, +#endif }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index f766dc9..24fe3ae 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -29,5 +29,6 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); - +unsigned long northbridge_write_acpi_tables(struct device *dev, + unsigned long current, struct acpi_rsdp *rsdp); #endif -- To view, visit https://review.coreboot.org/23821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Gerrit-Change-Number: 23821 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit February 2018