coreboot-gerrit February 2018

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Change in coreboot[master]: mb/google/kahlee: Use GPIO macros for baseboard
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23830 ) Change subject: mb/google/kahlee: Use GPIO macros for baseboard ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67748/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22250/ : SUCCESS -- To view, visit https://review.coreboot.org/23830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Gerrit-Change-Number: 23830 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 21:43:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Correct bad gpio entry
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23829 ) Change subject: mb/google/kahlee: Correct bad gpio entry ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67747/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22249/ : SUCCESS -- To view, visit https://review.coreboot.org/23829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Gerrit-Change-Number: 23829 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 21:39:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/amdfwtool/amdfwtool.c: Check fstat return
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23827 ) Change subject: util/amdfwtool/amdfwtool.c: Check fstat return ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67745/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22247/ : SUCCESS -- To view, visit https://review.coreboot.org/23827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6 Gerrit-Change-Number: 23827 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 21:37:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Add readable macros for GPIO
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23828 ) Change subject: soc/amd/stoneyridge: Add readable macros for GPIO ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67746/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22248/ : SUCCESS -- To view, visit https://review.coreboot.org/23828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Gerrit-Change-Number: 23828 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 21:37:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Use GPIO macros for baseboard
by Justin TerAvest (Code Review) 20 Feb '18

20 Feb '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23830 Change subject: mb/google/kahlee: Use GPIO macros for baseboard ...................................................................... mb/google/kahlee: Use GPIO macros for baseboard This commit uses newly defined macros to make it easier to read which iomux function pads are being configured to use. TEST=Booted grunt, confirmed display backlight came on. BUG=b:72875858 Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 71 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/23830/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index fb7ae96..f4329a1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -21,101 +21,98 @@ #include <stdlib.h> /* - * These settings were generated by a spreadsheet. If they need to be updated, - * update the spreadsheet shared with the Grunt development team. - * * As a rule of thumb, GPIO pins used by coreboot should be initialized at * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ - { GPIO_0, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP), /* GPIO_1 - SYS_RST_ODL */ - { GPIO_1, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_1, SYS_RESET_L, PULL_UP), /* GPIO_3 - MEM_VOLT_SEL */ - { GPIO_3, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_3, PULL_UP), /* GPIO_4 - EN_PP3300_WLAN */ - { GPIO_4, Function0, OUTPUT_H }, + PAD_GPO(GPIO_4, OUT_HIGH), /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - { GPIO_5, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_5, PULL_UP), /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - { GPIO_6, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_6, PULL_UP), /* GPIO_7 - APU_PWROK_OD (currently not used) */ - { GPIO_7, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_7, PULL_UP), /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ - { GPIO_8, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_8, PULL_UP), /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - { GPIO_9, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_9, PULL_UP), /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - { GPIO_11, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_11, PULL_UP), /* GPIO_14 - APU_HP_INT_ODL, SCI */ - { GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_14, PULL_UP), /* GPIO_15 - EC_IN_RW_OD */ - { GPIO_15, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_15, PULL_UP), /* GPIO_19 - APU_I2C_SCL3 (Touchscreen) */ - { GPIO_19, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), /* GPIO_20 - APU_I2C_SDA3 (Touchscreen) */ - { GPIO_20, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - { GPIO_21, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_21, PULL_UP), /* GPIO_22 - EC_SCI_ODL, SCI */ - { GPIO_22, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_22, PULL_UP), /* GPIO_23 - ACOK_OD */ /* GPIO_24 - USB_A1_OC_ODL */ - { GPIO_24, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_24, USB_OC3_L, PULL_UP), /* GPIO_25 - SD_CD */ - { GPIO_25, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_25, SD0_CD, PULL_UP), /* GPIO_26 - APU_PCIE_RST_L */ - { GPIO_26, Function0, INPUT }, + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* GPIO_40 - EMMC_BRIDGE_RST_L */ - { GPIO_40, Function0, OUTPUT_H }, + PAD_GPO(GPIO_24, OUT_HIGH), /* GPIO_42 - S5_MUX_CTRL */ - { GPIO_42, Function0, INPUT }, + PAD_NF(GPIO_42, S5_MUX_CTRL, PULL_NONE), /* GPIO_70 - WLAN_PE_RST_L */ - { GPIO_70, Function0, OUTPUT_H }, + PAD_GPO(GPIO_70, OUT_HIGH), /* GPIO_74 - LPC_CLK0_EC_R */ - { GPIO_74, Function0, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + PAD_NF(GPIO_74, LPCCLK0, PULL_DOWN), /* GPIO_84 - HUB_RST (Active High) */ - { GPIO_84, Function1, OUTPUT_L }, + PAD_GPO(GPIO_84, OUT_LOW), /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ - { GPIO_85, Function1, OUTPUT_L }, + PAD_GPO(GPIO_85, OUT_LOW), /* GPIO_87 - LPC_SERIRQ */ - { GPIO_87, Function0, INPUT }, + PAD_NF(GPIO_87, SERIRQ, PULL_NONE), /* GPIO_88 - LPC_CLKRUN_L */ - { GPIO_88, Function0, INPUT }, + PAD_NF(GPIO_88, LPC_CLKRUN_L, PULL_NONE), /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ - { GPIO_92, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP), /* GPIO_93 - EMMC_RST_L */ - { GPIO_93, Function1, OUTPUT_H }, + PAD_GPO(GPIO_93, OUT_HIGH), /* GPIO_95 - SD_CLK */ /* GPIO_96 - SD_CMD */ @@ -125,137 +122,137 @@ /* GPIO_100 - SD_D3 */ /* GPIO_101 - SD_WP_L */ - { GPIO_101, Function0, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + PAD_NF(GPIO_101, SD0_WP, PULL_DOWN), /* GPIO_116 - PCIE_EMMC_CLKREQ_L */ - { GPIO_116, Function0, INPUT }, + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), /* GPIO_117 - PCH_SPI_CLK_R */ /* GPIO_118 - PCH_SPI_CS0_L */ - { GPIO_118, Function0, INPUT }, + PAD_NF(GPIO_118, SPI_CS1_L, PULL_NONE), /* GPIO_119 - SPK_PA_EN */ - { GPIO_119, Function2, OUTPUT_H }, + PAD_GPO(GPIO_119, OUT_HIGH), /* GPIO_120 - PCH_SPI_MISO */ /* GPIO_121 - PCH_SPI_MOSI */ /* GPIO_122 - APU_BIOS_FLASH_WP_L */ - { GPIO_122, Function1, INPUT }, + PAD_GPI(GPIO_122, PULL_NONE), /* GPIO_126 - DMIC_CLK2_EN */ - { GPIO_126, Function1, OUTPUT_H }, + PAD_GPO(GPIO_126, OUT_HIGH), /* GPIO_129 - APU_KBRST_L */ - { GPIO_129, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_129, KBRST_L, PULL_UP), /* GPIO_131 - CONFIG_STRAP3 */ - { GPIO_131, Function3, INPUT }, + PAD_GPI(GPIO_131, PULL_NONE), /* GPIO_132 - CONFIG_STRAP4 */ - { GPIO_132, Function2, INPUT }, + PAD_GPI(GPIO_132, PULL_NONE), /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ - { GPIO_133, Function1, OUTPUT_L }, + PAD_GPO(GPIO_133, OUT_LOW), /* GPIO_136 - UART_PCH_RX_DEBUG_TX */ - { GPIO_136, Function0, INPUT }, + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), /* GPIO_137 - AUDIO_CLK_EN (Remove in EVT?) */ - { GPIO_137, Function1, OUTPUT_H }, + PAD_GPO(GPIO_137, OUT_HIGH), /* GPIO_138 - UART_PCH_TX_DEBUG_RX */ - { GPIO_138, Function0, INPUT }, + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* GPIO_139 - CONFIG_STRAP1 */ - { GPIO_139, Function1, INPUT }, + PAD_GPI(GPIO_139, PULL_NONE), /* GPIO_140 - I2S_BCLK_R (init to func0, used for I2S) */ - { GPIO_140, Function0, INPUT }, + PAD_NF(GPIO_140, UART1_CTS_L, PULL_NONE), /* GPIO_141 - I2S2_DATA_MIC2 (init to func0, used for I2S) */ - { GPIO_141, Function0, INPUT }, + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), /* GPIO_142 - CONFIG_STRAP2 */ - { GPIO_142, Function1, INPUT }, + PAD_GPI(GPIO_142, PULL_NONE), /* GPIO_143 - I2S2_DATA (init to func0, used for I2S) */ - { GPIO_143, Function0, INPUT }, + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), /* GPIO_144 - I2S_LR_R (init to func0, used for I2S) */ - { GPIO_144, Function0, INPUT }, + PAD_NF(GPIO_144, UART1_INTR, PULL_NONE), /* GPIO_145 - PCH_I2C_AUDIO_SCL */ - { GPIO_145, Function0, INPUT }, + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), /* GPIO_146 - PCH_I2C_AUDIO_SDA */ - { GPIO_146, Function0, INPUT }, + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), /* GPIO_147 - PCH_I2C_H1_TPM_SCL */ - { GPIO_147, Function0, INPUT }, + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), /* GPIO_148 - PCH_I2C_H1_TPM_SDA */ - { GPIO_148, Function0, INPUT }, + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), }; const static struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ - { GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* GPIO_10 - SLP_S0_L (currently not used) */ - { GPIO_10, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), /* GPIO_12 - Unused (TP126) */ - { GPIO_12, Function2, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_12, PULL_UP), /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */ - { GPIO_13, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_13, PULL_UP), /* GPIO_16 - USB_C0_OC_L */ - { GPIO_16, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_16, USB_OC0_L, PULL_UP), /* GPIO_17 - USB_C1_OC_L */ - { GPIO_17, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_17, USB_OC1_L, PULL_UP), /* GPIO_18 - USB_A0_OC_ODL */ - { GPIO_18, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), /* GPIO_67 - PEN_RESET */ - { GPIO_67, Function0, OUTPUT_L }, + PAD_GPO(GPIO_67, OUT_LOW), /* GPIO_75 - Unused (strap) (R139/R130) */ - { GPIO_75, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_75, PULL_UP), /* GPIO_76 - EN_PP3300_TOUCHSCREEN */ - { GPIO_76, Function0, OUTPUT_H }, + PAD_GPO(GPIO_76, OUT_HIGH), /* GPIO_86 - Unused (TP109) */ - { GPIO_86, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_86, PULL_UP), /* GPIO_90 - EN_PP3300_CAMERA */ - { GPIO_90, Function0, OUTPUT_H }, + PAD_GPO(GPIO_90, OUT_HIGH), /* GPIO_91 - EN_PP3300_TRACKPAD */ - { GPIO_91, Function1, OUTPUT_H }, + PAD_GPO(GPIO_91, OUT_HIGH), /* GPIO_102 - EN_SD_SOCKET_PWR */ - { GPIO_102, Function0, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + PAD_NF(GPIO_102, SD0_PWR_CTRL, PULL_DOWN), /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */ - { GPIO_113, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_113, I2C2_SCL, PULL_UP), /* GPIO_114 - APU_I2C_SDA2 (Pen & Trackpad) */ - { GPIO_114, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_NF(GPIO_114, I2C2_SDA, PULL_UP), /* GPIO_115 - Unused (TP127) */ - { GPIO_115, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_115, PULL_UP), /* GPIO_130 - Unused (TP55) */ - { GPIO_130, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_130, PULL_UP), /* GPIO_135 - Unused (TP128) */ - { GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + PAD_GPI(GPIO_135, PULL_UP), }; const __attribute__((weak)) -- To view, visit https://review.coreboot.org/23830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Gerrit-Change-Number: 23830 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: mb/google/kahlee: Correct bad gpio entry
by Justin TerAvest (Code Review) 20 Feb '18

20 Feb '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23829 Change subject: mb/google/kahlee: Correct bad gpio entry ...................................................................... mb/google/kahlee: Correct bad gpio entry There's no need to set the output enable here; this is already handled by the native function. I'm making this correction in this change to prevent the GPIO pin descriptions from getting confusing. BUG=b:72875858 TEST=Booted, confirmed S5_MUX_CTRL high with and without this change. Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/23829/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 1e1f34b..fb7ae96 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -91,7 +91,7 @@ { GPIO_40, Function0, OUTPUT_H }, /* GPIO_42 - S5_MUX_CTRL */ - { GPIO_42, Function0, OUTPUT_H }, + { GPIO_42, Function0, INPUT }, /* GPIO_70 - WLAN_PE_RST_L */ { GPIO_70, Function0, OUTPUT_H }, -- To view, visit https://review.coreboot.org/23829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Gerrit-Change-Number: 23829 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Add readable macros for GPIO
by Justin TerAvest (Code Review) 20 Feb '18

20 Feb '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23828 Change subject: soc/amd/stoneyridge: Add readable macros for GPIO ...................................................................... soc/amd/stoneyridge: Add readable macros for GPIO This commit defines a set of macros for defining GPIO configuration that are easier to read than the raw iomux function values used today. TEST=None BUG=b:72875858 Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 201 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/23828/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 84a4e84..5e5055a 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -142,6 +142,207 @@ #define GPIO_147 147 #define GPIO_148 148 +/* IOMUX function names and values generated from BKDG. */ +#define GPIO_0_PWR_BTN_L 0 +#define GPIO_0_GPIOxx 1 +#define GPIO_1_SYS_RESET_L 0 +#define GPIO_1_GPIOxx 1 +#define GPIO_2_WAKE_L 0 +#define GPIO_2_GPIOxx 1 +#define GPIO_3_GPIOxx 0 +#define GPIO_4_GPIOxx 0 +#define GPIO_5_GPIOxx 0 +#define GPIO_5_DEVSLP0_S5 1 +#define GPIO_6_GPIOxx 0 +#define GPIO_6_LDT_RST_L 1 +#define GPIO_7_GPIOxx 0 +#define GPIO_7_LDT_PWROK 1 +#define GPIO_8_GPIOxx 0 +#define GPIO_8_SerPortTX_OUT 1 +#define GPIO_9_GPIOxx 0 +#define GPIO_9_SerPortRX_OUT 1 +#define GPIO_10_S0A3_GPIO 0 +#define GPIO_10_GPIOxx 1 +#define GPIO_11_GPIOxx 0 +#define GPIO_11_USB_OC7_L 1 +#define GPIO_12_IR_LED_L 0 +#define GPIO_12_LLB_L 1 +#define GPIO_12_GPIOxx 2 +#define GPIO_13_USB_OC5_L 0 +#define GPIO_13_GPIOxx 1 +#define GPIO_14_USB_OC6_L 0 +#define GPIO_14_GPIOxx 1 +#define GPIO_15_IR_RX1 0 +#define GPIO_15_GPIOxx 1 +#define GPIO_16_USB_OC0_L 0 +#define GPIO_16_TRST_L 1 +#define GPIO_16_GPIOxx 2 +#define GPIO_17_USB_OC1_L 0 +#define GPIO_17_TDI 1 +#define GPIO_17_GPIOxx 2 +#define GPIO_18_USB_OC2_L 0 +#define GPIO_18_TCK 1 +#define GPIO_18_GPIOxx 2 +#define GPIO_19_SCL1 0 +#define GPIO_19_I2C3_SCL 1 +#define GPIO_19_GPIOxx 2 +#define GPIO_20_SDA1 0 +#define GPIO_20_I2C3_SDA 1 +#define GPIO_20_GPIOxx 2 +#define GPIO_21_LPC_PD_L 0 +#define GPIO_21_GPIOxx 1 +#define GPIO_22_LPC_PME_L 0 +#define GPIO_22_GPIOxx 1 +#define GPIO_23_USB_OC4_L 0 +#define GPIO_23_IR_RX0 1 +#define GPIO_23_GPIOxx 2 +#define GPIO_24_USB_OC3_L 0 +#define GPIO_24_GPIOxx 1 +#define GPIO_25_SD0_CD 0 +#define GPIO_25_GPIOxx 1 +#define GPIO_26_PCIE_RST_L 0 +#define GPIO_26_GPIOxx 1 +#define GPIO_39_VDDGFX_PD 0 +#define GPIO_39_GPIOxx 1 +#define GPIO_40_GPIOxx 0 +#define GPIO_42_S5_MUX_CTRL 0 +#define GPIO_42_GPIOxx 1 +#define GPIO_64_GPIOxx 0 +#define GPIO_65_GPIOxx 0 +#define GPIO_66_GPIOxx 0 +#define GPIO_66_ShutDown_L 1 +#define GPIO_67_GPIOxx 0 +#define GPIO_67_DEVSLP0 1 +#define GPIO_68_GPIOxx 0 +#define GPIO_68_SGPIO_CLK 1 +#define GPIO_69_GPIOxx 0 +#define GPIO_69_SGPIO_LOAD 1 +#define GPIO_70_GPIOxx 0 +#define GPIO_70_DEVSLP1 1 +#define GPIO_71_GPIOxx 0 +#define GPIO_71_SGPIO_DATAOUT 1 +#define GPIO_72_GPIOxx 0 +#define GPIO_72_SGPIO_DATAIN 1 +#define GPIO_74_LPCCLK0 0 +#define GPIO_74_GPIOxx 1 +#define GPIO_75_LPCCLK1 0 +#define GPIO_75_GPIOxx 1 +#define GPIO_76_GPIOxx 0 +#define GPIO_76_SPI_TPM_CS_L 1 +#define GPIO_84_FANIN0 0 +#define GPIO_84_GPIOxx 1 +#define GPIO_85_FANOUT0 0 +#define GPIO_85_GPIOxx 1 +#define GPIO_86_GPIOxx 1 +#define GPIO_87_SERIRQ 0 +#define GPIO_87_GPIOxx 1 +#define GPIO_88_LPC_CLKRUN_L 0 +#define GPIO_88_GPIOxx 1 +#define GPIO_89_GPIOxx 0 +#define GPIO_90_GPIOxx 0 +#define GPIO_91_SPKR 0 +#define GPIO_91_GPIOxx 1 +#define GPIO_92_CLK_REQ0_L 0 +#define GPIO_92_SATA_IS0_L 1 +#define GPIO_92_SATA_ZP0_L 2 +#define GPIO_92_GPIOxx 3 +#define GPIO_93_SD0_LED 0 +#define GPIO_93_GPIOxx 1 +#define GPIO_95_GPIOxx 0 +#define GPIO_96_GPIOxx 0 +#define GPIO_97_GPIOxx 0 +#define GPIO_98_GPIOxx 0 +#define GPIO_99_GPIOxx 0 +#define GPIO_100_GPIOxx 0 +#define GPIO_101_SD0_WP 0 +#define GPIO_101_GPIOxx 1 +#define GPIO_102_SD0_PWR_CTRL 0 +#define GPIO_102_GPIOxx 1 +#define GPIO_113_SCL0 0 +#define GPIO_113_I2C2_SCL 1 +#define GPIO_113_GPIOxx 2 +#define GPIO_114_SDA0 0 +#define GPIO_114_I2C2_SDA 1 +#define GPIO_114_GPIOxx 2 +#define GPIO_115_CLK_REQ1_L 0 +#define GPIO_115_GPIOxx 1 +#define GPIO_116_CLK_REQ2_L 0 +#define GPIO_116_GPIOxx 1 +#define GPIO_117_ESPI_CLK 0 +#define GPIO_117_GPIOxx 1 +#define GPIO_118_SPI_CS1_L 0 +#define GPIO_118_GPIOxx 1 +#define GPIO_119_SPI_CS2_L 0 +#define GPIO_119_ESPI_CS_L 1 +#define GPIO_119_GPIOxx 2 +#define GPIO_120_ESPI_DAT1 0 +#define GPIO_120_GPIOxx 1 +#define GPIO_121_ESPI_DAT0 0 +#define GPIO_121_GPIOxx 1 +#define GPIO_122_ESPI_DAT2 0 +#define GPIO_122_GPIOxx 1 +#define GPIO_126_GA20IN 0 +#define GPIO_126_GPIOxx 1 +#define GPIO_129_KBRST_L 0 +#define GPIO_129_GPIOxx 1 +#define GPIO_130_SATA_ACT_L 0 +#define GPIO_130_GPIOxx 1 +#define GPIO_131_CLK_REQ3_L 0 +#define GPIO_131_SATA_IS1_L 1 +#define GPIO_131_SATA_ZP1_L 2 +#define GPIO_131_GPIOxx 3 +#define GPIO_132_CLK_REQG_L 0 +#define GPIO_132_OSCIN 1 +#define GPIO_132_GPIOxx 2 +#define GPIO_133_ESPI_DAT3 0 +#define GPIO_133_GPIOxx 1 +#define GPIO_135_UART0_CTS_L 0 +#define GPIO_135_GPIOxx 1 +#define GPIO_136_UART0_RXD 0 +#define GPIO_136_GPIOxx 1 +#define GPIO_137_UART0_RTS_L 0 +#define GPIO_137_GPIOxx 1 +#define GPIO_138_UART0_TXD 0 +#define GPIO_138_GPIOxx 1 +#define GPIO_139_UART0_INTR 0 +#define GPIO_139_GPIOxx 1 +#define GPIO_140_UART1_CTS_L 0 +#define GPIO_140_GPIOxx 1 +#define GPIO_141_UART1_RXD 0 +#define GPIO_141_GPIOxx 1 +#define GPIO_142_UART1_RTS_L 0 +#define GPIO_142_GPIOxx 1 +#define GPIO_143_UART1_TXD 0 +#define GPIO_143_GPIOxx 1 +#define GPIO_144_UART1_INTR 0 +#define GPIO_144_GPIOxx 1 +#define GPIO_145_I2C0_SCL 0 +#define GPIO_145_GPIOxx 1 +#define GPIO_146_I2C0_SDA 0 +#define GPIO_146_GPIOxx 1 +#define GPIO_147_I2C1_SCL 0 +#define GPIO_147_GPIOxx 1 +#define GPIO_148_I2C1_SDA 0 +#define GPIO_148_GPIOxx 1 + +#define GPIO_OUTPUT_OUT_HIGH (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW FCH_GPIO_OUTPUT_ENABLE + +#define GPIO_PULL_PULL_UP FCH_GPIO_PULL_UP_ENABLE +#define GPIO_PULL_PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 + +/* Native function pad configuration */ +#define PAD_NF(pin, func, pull) \ + {pin, pin ## _ ## func, GPIO_PULL ## _ ## pull} +/* General purpose input pad configuration */ +#define PAD_GPI(pin, pull) \ + {pin, pin ## _ ## GPIOxx, GPIO_PULL ## _ ## pull} +/* General purpose output pad configuration */ +#define PAD_GPO(pin, direction) \ + {pin, pin ## _ ## GPIOxx, GPIO_OUTPUT ## _ ## direction} + typedef uint32_t gpio_t; + #endif /* __ACPI__ */ #endif /* __STONEYRIDGE_GPIO_H__ */ -- To view, visit https://review.coreboot.org/23828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Gerrit-Change-Number: 23828 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

1 0

Change in coreboot[master]: util/amdfwtool/amdfwtool.c: Check fstat return
by Richard Spiegel (Code Review) 20 Feb '18

20 Feb '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/23827 Change subject: util/amdfwtool/amdfwtool.c: Check fstat return ...................................................................... util/amdfwtool/amdfwtool.c: Check fstat return Funtion fstat will return -1 if there's any error, 0 if successful. Check that fstat return is equal to 0, print error message and exit if not 0. This fixes CIDs 1353018 and 1353020 BUG=b:72062481 TEST=Build no errors Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/23827/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 303a31d..406ae05 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -298,7 +298,11 @@ free(base); exit(1); } - fstat(fd, &fd_stat); + if (fstat(fd, &fd_stat)) { + printf("fstat error: %s\n", strerror(errno)); + free(base); + exit(1); + } switch (fw_table[i].type) { case AMD_FW_IMC: @@ -369,7 +373,11 @@ free(base); exit(1); } - fstat(fd, &fd_stat); + if (fstat(fd, &fd_stat)) { + printf("fstat error: %s\n", strerror(errno)); + free(base); + exit(1); + } pspdir[4+4*i+1] = (uint32_t)fd_stat.st_size; pspdir[4+4*i+2] = pos + rom_base_address; -- To view, visit https://review.coreboot.org/23827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83284d9125c75a29471f213f88b9181d5edba2e6 Gerrit-Change-Number: 23827 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mainboard/google/zoombini: Add config for meowth audio
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23334 ) Change subject: mainboard/google/zoombini: Add config for meowth audio ...................................................................... Patch Set 19: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67744/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22246/ : SUCCESS -- To view, visit https://review.coreboot.org/23334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9 Gerrit-Change-Number: 23334 Gerrit-PatchSet: 19 Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 20:57:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/broadwell: Enable VT-d and X2APIC
by build bot (Jenkins) (Code Review) 20 Feb '18

20 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23820 ) Change subject: soc/intel/broadwell: Enable VT-d and X2APIC ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67742/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/22244/ : SUCCESS -- To view, visit https://review.coreboot.org/23820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Gerrit-Change-Number: 23820 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Feb 2018 20:26:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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