coreboot-gerrit February 2018

coreboot-gerrit@coreboot.org

1 participants
1573 discussions

Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67032/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21605/ : SUCCESS -- To view, visit https://review.coreboot.org/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 17:27:54 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mainboard/cubietech/cubieboard: Fix checkpatch warnings
by Martin Roth (Code Review) 05 Feb '18

05 Feb '18

Martin Roth has abandoned this change. ( https://review.coreboot.org/19118 ) Change subject: mainboard/cubietech/cubieboard: Fix checkpatch warnings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/19118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I79a822a5797ea681c4b4ec00dcf8e82783c875d2 Gerrit-Change-Number: 19118 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23540 ) Change subject: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67031/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21604/ : SUCCESS -- To view, visit https://review.coreboot.org/23540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Gerrit-Change-Number: 23540 Gerrit-PatchSet: 4 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 11:55:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/cannonlake: Implement Sata SOC override as per CNP-PCH
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23591 ) Change subject: soc/intel/cannonlake: Implement Sata SOC override as per CNP-PCH ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67030/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21603/ : SUCCESS -- To view, visit https://review.coreboot.org/23591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Gerrit-Change-Number: 23591 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 11:50:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/common/block: Add SoC overrides for SATA initialization
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23589 ) Change subject: soc/intel/common/block: Add SoC overrides for SATA initialization ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67028/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21601/ : SUCCESS -- To view, visit https://review.coreboot.org/23589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Gerrit-Change-Number: 23589 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 11:45:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23590 ) Change subject: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67029/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21602/ : SUCCESS -- To view, visit https://review.coreboot.org/23590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I497e367f4b1dd83130c137965df906abf3b8ae0f Gerrit-Change-Number: 23590 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 11:40:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: soc/intel/cannonlake: Implement Sata SOC override as per CNP-PCH
by Subrata Banik (Code Review) 05 Feb '18

05 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23591 Change subject: soc/intel/cannonlake: Implement Sata SOC override as per CNP-PCH ...................................................................... soc/intel/cannonlake: Implement Sata SOC override as per CNP-PCH This patch ensures soc/sata.c correctly translate pci config offset 0x92 bit 0-2. Bit 0-2 SATA Port x Present (SPDx) 0 = Port x is enabled 1 = Port x is disabled Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/sata.c 2 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/23591/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 47f06aa..76f31b2 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c diff --git a/src/soc/intel/cannonlake/sata.c b/src/soc/intel/cannonlake/sata.c new file mode 100644 index 0000000..324a0d9 --- /dev/null +++ b/src/soc/intel/cannonlake/sata.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <intelblocks/sata.h> +#include <soc/pci_devs.h> + +#define SATA_ABAR_PORT_IMPLEMENTED 0x0c +#define SATA_PCI_CFG_PORT_CTL_STS 0x92 + +static void *get_ahci_bar(device_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. By default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and slumber states + * and can detect devices. When disabled, the port is in the off state and + * can't detect any devices. + */ +void sata_soc_final(device_t dev) +{ + void *ahcibar = get_ahci_bar(dev); + u32 port_impl, temp; + + /* Set Bus Master */ + temp = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + + /* Read Ports Implemented (GHC_PI) */ + port_impl = ~read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07; + /* Port enable */ + temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp |= port_impl; + pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); +} -- To view, visit https://review.coreboot.org/23591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Gerrit-Change-Number: 23591 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH
by Subrata Banik (Code Review) 05 Feb '18

05 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23590 Change subject: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH ...................................................................... soc/intel/skylake: Implement Sata SOC override as per SPT-PCH This patch ensures soc/sata.c correctly translate pci config offset 0x92 bit 0-2. Bit 0-2 Port x Enabled (PxE) 0 = Disabled. The Port is in the 'off' state and can't detect any devices. 1 = Enabled. The port can detect devices. Change-Id: I497e367f4b1dd83130c137965df906abf3b8ae0f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/sata.c 2 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/23590/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef95cf7..0c7355a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c ramstage-y += sd.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c new file mode 100644 index 0000000..d7b6215 --- /dev/null +++ b/src/soc/intel/skylake/sata.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <intelblocks/sata.h> +#include <soc/pci_devs.h> + +#define SATA_ABAR_PORT_IMPLEMENTED 0x0c +#define SATA_PCI_CFG_PORT_CTL_STS 0x92 + +static void *get_ahci_bar(device_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. By default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and slumber states + * and can detect devices. When disabled, the port is in the off state and + * can't detect any devices. + */ +void sata_soc_final(device_t dev) +{ + void *ahcibar = get_ahci_bar(dev); + u32 port_impl, temp; + + /* Set Bus Master */ + temp = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); + + /* Read Ports Implemented (GHC_PI) */ + port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07; + /* Port enable */ + temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp |= port_impl; + pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); +} -- To view, visit https://review.coreboot.org/23590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I497e367f4b1dd83130c137965df906abf3b8ae0f Gerrit-Change-Number: 23590 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/common/block: Add SoC overrides for SATA initialization
by Subrata Banik (Code Review) 05 Feb '18

05 Feb '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23589 Change subject: soc/intel/common/block: Add SoC overrides for SATA initialization ...................................................................... soc/intel/common/block: Add SoC overrides for SATA initialization SATA PCH configuration space registers bit mapping is different for various SOCs hence common API between SPT-PCH and CNL-PCH causing issue. Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/sata.h M src/soc/intel/common/block/sata/sata.c 2 files changed, 27 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/23589/1 diff --git a/src/soc/intel/common/block/include/intelblocks/sata.h b/src/soc/intel/common/block/include/intelblocks/sata.h new file mode 100644 index 0000000..c726cea --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/sata.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_SATA_H +#define SOC_INTEL_COMMON_BLOCK_SATA_H + +/* SoC override SATA final initialization */ +void sata_soc_final(device_t dev); + +#endif /* SOC_INTEL_COMMON_BLOCK_SATA_H */ diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 791510e..f6a0a44 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -17,52 +17,20 @@ #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <intelblocks/sata.h> #include <soc/pci_devs.h> -#define SATA_ABAR_PORT_IMPLEMENTED 0x0c -#define SATA_PCI_CFG_PORT_CTL_STS 0x92 - -static void *get_ahci_bar(void) +/* SoC override SATA final initialization */ +__attribute__((weak)) void sata_soc_final(device_t dev) { - uintptr_t bar; - device_t dev = PCH_DEV_SATA; - - bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); -} - -/* - * SATA Port control and Status. By default, the SATA ports are set (by HW) - * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial - * power on reset. When enabled by software as per SATA port mapping, - * the ports can transition between the on, partial and slumber states - * and can detect devices. When disabled, the port is in the off state and - * can't detect any devices. - */ -static void sata_final(device_t dev) -{ - void *ahcibar = get_ahci_bar(); - u32 port_impl, temp; - - dev = PCH_DEV_SATA; - - /* Set Bus Master */ - temp = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER); - - /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07; - /* Port enable */ - temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS); - temp |= port_impl; - pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); + /* no-op */ } static struct device_operations sata_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .final = sata_final, + .final = &sata_soc_final, .ops_pci = &pci_dev_ops_pci, }; -- To view, visit https://review.coreboot.org/23589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Gerrit-Change-Number: 23589 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC confi...
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23230 ) Change subject: soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67027/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21600/ : SUCCESS -- To view, visit https://review.coreboot.org/23230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Gerrit-Change-Number: 23230 Gerrit-PatchSet: 9 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 09:04:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2018