coreboot-gerrit February 2018

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67038/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21609/ : SUCCESS -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 20:39:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23580 ) Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67037/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/21608/ : ABORTED -- To view, visit https://review.coreboot.org/23580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047 Gerrit-Change-Number: 23580 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 20:34:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23594 ) Change subject: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67036/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21607/ : SUCCESS -- To view, visit https://review.coreboot.org/23594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Gerrit-Change-Number: 23594 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 20:28:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22
by Furquan Shaikh (Code Review) 05 Feb '18

05 Feb '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/23594 Change subject: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 ...................................................................... mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/23594/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 348f7de..0149f28 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -5,7 +5,7 @@ register "deep_s3_enable_dc" = "1" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -291,7 +291,7 @@ device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 on chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" + register "wake" = "GPE0_DW2_22" device pci 00.0 on end end end # PCI Express Port 4 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index dbee643..e85d948 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -253,8 +253,8 @@ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ + PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), /* E23 : DDPD_CTRLDATA ==> NC */ PAD_CFG_NC(GPP_E23), -- To view, visit https://review.coreboot.org/23594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Gerrit-Change-Number: 23594 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23592 ) Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67035/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21606/ : SUCCESS -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 18:27:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC confi...
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23230 ) Change subject: soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/67033/ : SUCCESS -- To view, visit https://review.coreboot.org/23230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Gerrit-Change-Number: 23230 Gerrit-PatchSet: 10 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 18:16:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23592 ) Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... Patch Set 1: No Builds Executed -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 18:16:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by build bot (Jenkins) (Code Review) 05 Feb '18

05 Feb '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23592 ) Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/67034/ : ABORTED -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Feb 2018 18:16:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by Arthur Heymans (Code Review) 05 Feb '18

05 Feb '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/23592 ) Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... cpu/intel/sandybridge: Put stage cache into TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/model_206ax.h A src/cpu/intel/model_206ax/stage_cache.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/sandybridge.h 6 files changed, 64 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23592/2 -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG
by Arthur Heymans (Code Review) 05 Feb '18

05 Feb '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23592 Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ...................................................................... cpu/intel/sandybridge: Put stage cache into TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23592/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f16b119..09311d1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -22,6 +22,7 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string @@ -35,4 +36,12 @@ hex default 0x800000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 7516e9d..1e04554 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -11,6 +11,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 594dde1..9a50e2b 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -92,6 +92,26 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x800000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif +#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) +# error "CONFIG_IED_REGION_SIZE is not a power of 2" +#endif + #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index da43de0..e80fa31 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -132,6 +132,10 @@ params->ied_base = tsegmb + params->smram_size; params->ied_size = tseg_size - params->smram_size; + /* Adjust available SMM handler memory size. */ + if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1f56585..d446049 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -40,7 +40,8 @@ #define IVB_STEP_D0 (BASE_REV_IVB + 6) /* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 + +#define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ -- To view, visit https://review.coreboot.org/23592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Gerrit-Change-Number: 23592 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit February 2018