Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30385 )
Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
......................................................................
Patch Set 9: Code-Review+1
patchset tested on google/guado
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Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30144 )
Change subject: mb/google/octopus: Override emmc DLL values for Phaser
......................................................................
Patch Set 2:
ODM validation is pass.
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Kane Chen has uploaded a new patch set (#2) to the change originally created by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/30144 )
Change subject: mb/google/octopus: Override emmc DLL values for Phaser
......................................................................
mb/google/octopus: Override emmc DLL values for Phaser
New emmc DLL values for Phaser.
BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test
Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
1 file changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30144/2
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30180 )
Change subject: mainboard/google/poppy/variants/rammus: Fixed touchscreen function failed
......................................................................
Patch Set 11: Code-Review+2
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Change subject: mainboard/google/poppy/variants/rammus: Fixed touchscreen function failed
......................................................................
Patch Set 11: Code-Review+1
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Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30385
to look at the new patch set (#9).
Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
......................................................................
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootblock.c
M src/mainboard/google/jecht/romstage.c
M src/soc/intel/broadwell/bootblock/pch.c
A src/soc/intel/broadwell/include/soc/bootblock.h
M src/soc/intel/broadwell/romstage/pch.c
M src/soc/intel/broadwell/romstage/romstage.c
M src/superio/ite/Makefile.inc
M src/superio/ite/it8772f/Makefile.inc
9 files changed, 110 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/9
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Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30384
to look at the new patch set (#9).
Change subject: nb/intel/broadwell: Add an option for where verstage starts
......................................................................
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/auron/Makefile.inc
M src/mainboard/google/jecht/Makefile.inc
M src/mainboard/intel/wtm2/Makefile.inc
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/romstage/raminit.c
6 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/9
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30272 )
Change subject: nb/intel/haswell: Add support for PCIe graphics
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/30272/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/30272/6//COMMIT_MSG@11
PS6, Line 11: *The first path*: If it's okay for the IGD to be disabled, the link
: training is done in early romstage. The MRC will then set (and lock)
: GGC, and, if there is a device of VGA class present in a PEG slot,
: disable the IGD:
:
: Before the MRC: GGC = 0x0208, DEVEN = 0x00000039.
: After the MRC: GGC = 0x0003, DEVEN = 0x00000029.
:
: *The second path*: If the IGD needs to be kept enabled, the link
: training is done in ramstage. This is because the MRC will always
: disable the IGD if there is a device of VGA class in a PEG slot, but
: it can't see the device until link training is done.
:
: The second path can, unfortunately, lead to an increase in boot time, as
: the training needs to be complete before the PEG bus is scanned. When
: there are multiple PEG devices, the training occurs in parallel, limiting
: the impact on boot time.
Would the following work?
- do link training in romstage.
- Setup the bridge and if you find a VGA class, disable that PEG with DEVEN, unless you have no IGD
- re-enable that PEG after the mrc.bin has run. (not sure if trainig is needed again)
That would provide a more unified flow and avoid different paths.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30271 )
Change subject: nb/intel/haswell: Handle boards that do not support IGD
......................................................................
Patch Set 3: Code-Review+2
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