coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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1832 discussions

Change in ...coreboot[master]: sb/intel/i82801gx: Autodisable functions based on devicetree
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30244 ) Change subject: sb/intel/i82801gx: Autodisable functions based on devicetree ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/30244/12/src/southbridge/intel/i82801gx/i82… File src/southbridge/intel/i82801gx/i82801gx.c: https://review.coreboot.org/#/c/30244/12/src/southbridge/intel/i82801gx/i82… PS12, Line 25: switch (devfn) { > why is internal lan missing ? The internal LAN is on the bus behind the PCI bridge afaict from the datasheets. No coreboot device is using it, so it was easier to still disable it in the romstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/30244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Gerrit-Change-Number: 30244 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Dec 2018 19:25:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x200: Remove RCBA replay
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30402 ) Change subject: mb/lenovo/x200: Remove RCBA replay ...................................................................... Patch Set 2: I actually checked all the documented registers. Things like RPFN, IOTRAP, ... don't need to be configured here. -- To view, visit https://review.coreboot.org/c/coreboot/+/30402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Gerrit-Change-Number: 30402 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Dec 2018 18:27:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x200: Remove RCBA replay
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Hello Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30402 to look at the new patch set (#2). Change subject: mb/lenovo/x200: Remove RCBA replay ...................................................................... mb/lenovo/x200: Remove RCBA replay This either sets unwanted or unnecessary settings. Tested. Everything still works fine. Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/romstage.c 1 file changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30402/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Gerrit-Change-Number: 30402 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/lenovo/x200: Remove RCBA replay
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30402 Change subject: mb/lenovo/x200: Remove RCBA replay ...................................................................... mb/lenovo/x200: Remove RCBA replay This either sets unwanted or unnecessary settings. Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/romstage.c 1 file changed, 0 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30402/1 diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 8176fad..2cd1b21 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -119,39 +119,6 @@ i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; - /* Enable ethernet. */ - RCBA32(0x3414) &= ~0x20; - - RCBA32(0x0238) = 0x00543210; - RCBA32(0x0240) = 0x009c0b02; - RCBA32(0x0244) = 0x00a20b1a; - RCBA32(0x0248) = 0x005402cb; - RCBA32(0x0254) = 0x00470966; - RCBA32(0x0258) = 0x00470473; - RCBA32(0x0260) = 0x00e90825; - RCBA32(0x0278) = 0x00bc0efb; - RCBA32(0x027c) = 0x00c00f0b; - RCBA32(0x0280) = 0x00670000; - RCBA32(0x0284) = 0x006d0000; - RCBA32(0x0288) = 0x00600b4e; - RCBA32(0x1e10) = 0x00020800; - RCBA32(0x1e18) = 0x36ea00a0; - RCBA32(0x1e80) = 0x000c0801; - RCBA32(0x1e84) = 0x000200f0; - RCBA32(0x2028) = 0x04c8f95e; - RCBA32(0x202c) = 0x055c095e; - RCBA32(0x204c) = 0x001ffc00; - RCBA32(0x2050) = 0x00100fff; - RCBA32(0x2090) = 0x37000000; - RCBA32(0x20b0) = 0x0c000000; - RCBA32(0x20d0) = 0x09000000; - RCBA32(0x20f0) = 0x05000000; - RCBA32(0x3400) = 0x0000001c; - RCBA32(0x3410) = 0x00100461; - RCBA32(0x3414) = 0x00000000; - RCBA32(0x341c) = 0xbf4f001f; - RCBA32(0x3420) = 0x00000000; - RCBA32(0x3430) = 0x00000001; init_iommu(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f552dea1b37cdc17c9dd26a0294b59063cdc2be Gerrit-Change-Number: 30402 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: Fix typo in GPIO Level
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30401 Change subject: sb/intel/bd82x6x: Fix typo in GPIO Level ...................................................................... sb/intel/bd82x6x: Fix typo in GPIO Level Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/acpi/pch.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/30401/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index a068bc0..71eda65 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -87,7 +87,7 @@ GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 1, + GP00, 1, GP01, 1, GP02, 1, GP03, 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/30401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2 Gerrit-Change-Number: 30401 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] mb/lenovo/dock.asl: Add proper dock support
by Arthur Heymans (Code Review) 23 Dec '18

23 Dec '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30397 Change subject: [WIP] mb/lenovo/dock.asl: Add proper dock support ...................................................................... [WIP] mb/lenovo/dock.asl: Add proper dock support Todo: - Add parallel port and serial port ACPI code - Clean up. A lot of code is slightly modified vendor code which isn't that well written. Also lots of unneeded regs presented here. Working: - Dock LED - Docking and undocking events Change-Id: Ifa4a5a0272c6d3ec0b65871e5c1448d395bc74a8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/acpi/dock.asl 1 file changed, 308 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/30397/1 diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index 4a0ccf3..b71e4e3 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -14,60 +14,338 @@ * GNU General Public License for more details. */ -Scope (\_SB) +#include "dock.h" + +Scope(\_SB.PCI0.LPCB) { - Device(DOCK) + OperationRegion (NCFG, SystemIO, 0x2E, 0x02) + Field (NCFG, ByteAcc, NoLock, Preserve) { - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + INDX, 8, + DATA, 8 + } - Method(_DCK, 1, NotSerialized) + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, + Offset (0x20), + SIOD, 8, + Offset (0x22), + SCF2, 8, + Offset (0x24), + SCF4, 8, + , 2, + PPSE, 1, + , 4, + PNF, 1, + FDCD, 1, + PPD, 1, + SP2D, 1, + SP1D, 1, + , 1, + GPSR, 2, + Offset (0x27), + SRID, 8, + Offset (0x29), + SCF9, 8, + Offset (0x2B), + Offset (0x30), + LDA, 1, + Offset (0x31), + Offset (0x60), + IOHI, 8, + IOLW, 8, + Offset (0x70), + IRQN, 4, + IRQW, 1, + Offset (0x71), + IRQT, 1, + IRQL, 1, + Offset (0x72), + Offset (0x74), + DMA0, 3, + Offset (0x75), + DMA1, 3, + Offset (0x76) + } + + IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0xF0), + GPPS, 8, + GPPC, 8, + GPER, 8 + } + + Method(LCON, 1, NotSerialized) + { + if (Arg0) { - if (Arg0) { - /* connect dock */ - Store (1, \GP28) - Store (1, \_SB.PCI0.LPCB.EC.DKR1) - } else { - /* disconnect dock */ - Store (0, \GP28) - Store (0, \_SB.PCI0.LPCB.EC.DKR1) + if (\_SB.PCI0.LPCB.EC.DPWR) + { + \_SB.DOCK.DLPD = 0x01 + \_SB.DOCK.DLPC = 0x07 + While (!(0x08 & \_SB.DOCK.DLPC)) + { + Sleep(0x01) + } + + \_SB.DOCK.DRST = 0x01 + if ((SIOD != 0xff)) + { + /* Enable 14.318MHz CLK on CLKIN */ + SCF9 |= 0xa0 + While (!(0x10 & SCF9)) + { + Sleep (0x01) + } + /* set GPIO pins to Serial/Parallel Port functions */ + SCF2 |= 0xeb + LDN = 0x07 /* r_gpio */ + Local0 = (0x1620 & 0xff) + IOLW = Local0 + Local0 = (0x1620 >> 0x8) + IOHI = (Local0 & 0xff) + GPPS = 0x01 + GPPC = 0x03 + GPPS = 0x02 + GPPC = 0x03 + \_SB.DOCK.DUSB = 0 + + } + } - Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) - Return (Local0) } - - Method(_STA, 0, NotSerialized) + else { - Return (\_SB.PCI0.LPCB.EC.DKR1) + \_SB.DOCK.DUSB = 1 + \_SB.DOCK.DRST = 0 + \_SB.DOCK.DLPD = 0 + \_SB.DOCK.DLPC = 0 } } } -Scope(\_SB.PCI0.LPCB.EC) +Scope (\_SB) { - Method(_Q18, 0, NotSerialized) + Device(DOCK) { - Notify(\_SB.DOCK, 3) + OperationRegion (NSDL, SystemIO, DLPC_CONTROL, 0x01) + Field (NSDL, ByteAcc, NoLock, Preserve) + { + DLPC, 8 + } + + OperationRegion (NSIO, SystemIO, DLPC_GPIO_BASE, 0x0C) + Field (NSIO, ByteAcc, NoLock, Preserve) + { + DRST, 1, + DLPD, 1, + ULRT, 1, + ULPD, 1, + Offset (0x01), + , 4, + DKI0, 1, + Offset (0x02), + Offset (0x09), + DKI1, 1, + DKI2, 1 + } + + OperationRegion (DSIO, SystemIO, DOCK_GPIO_BASE, 0x0C) + Field (DSIO, ByteAcc, NoLock, Preserve) + { + , 1, + DUSB, 1, + Offset (0x01) + } + + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + Name (G_ID, 0xffffffff) + Name (DOID, 0xffffffff) + + Method (GDID, 0, NotSerialized) + { + If ((DOID == 0xFFFFFFFF)) + { + \_SB.DOCK.G_ID = 0xFFFFFFFF + DOID = RDID () + } + + Return (DOID) /* \_SB_.DOCK.DOID */ + } + + Method (RDID, 0, NotSerialized) + { + Local0 = 0x00 + If (\_SB.PCI0.LPCB.EC.DPWR) + { + If ((\_SB.DOCK.GGID () == 0x00)) + { + Local0 = 0x4C004D24 + } + + If ((\_SB.DOCK.GGID () == 0x01)) + { + Local0 = 0x44004D24 + } + } + Return (Local0) + } + + Method (GGID, 0, NotSerialized) + { + Local0 = G_ID + If ((Local0 == 0xFFFFFFFF)) + { + Local0 = DKI0 + Local1 = DKI1 + Local2 = DKI2 + Local0 |= (Local1 << 0x01) + Local0 |= (Local2 << 0x02) + G_ID = Local0 + } + return (Local0) + } + + Method (_STA, 0, NotSerialized) + { + Debug = "Dock Status" + Local0 = GGID () + Local1 = 0x00 + if ((Local0 == 0) || (Local0 == 1)) + { + if ((GDID () == 0x4C004D24) || (GDID () == 0x44004D24)) + { + Local1 = 0x0f + } + } + Debug = Local1 + return (Local1) + } + + Method (DDCK, 1, NotSerialized) + { + If (Arg0) + { + \_SB.PCI0.LPCB.EC.LEDS = 0x08 + \_SB.PCI0.LPCB.EC.LEDS = 0x89 + \_SB.PCI0.LPCB.LCON (0x01) + } + Else + { + \_SB.PCI0.LPCB.EC.LEDS = 0x88 + \_SB.PCI0.LPCB.EC.LEDS = 0xc9 + \_SB.PCI0.LPCB.LCON (0x00) + } + + Return (0x01) + } + + Method (_DCK, 1, NotSerialized) + { + Debug = "_DCK" + Debug = Arg0 + Local0 = 0x0 + If ((GGID () == 0x0) || (GGID () == 1)) + { + Local0 = DDCK(Arg0) + } + Return (Local0) + } + + Method (_EJ0, 1, NotSerialized) + { + Local0 = GGID () + If ((Local0 == 0) || (Local0 == 1)) + { + if (Arg0) + { + DOID = 0 + } + \_SB.PCI0.LPCB.EC.LEDS = 0x08 + \_SB.PCI0.LPCB.EC.LEDS = 0x09 + } + } + } +} + + Scope(\_SB.PCI0.LPCB.EC) +{ + OperationRegion(PMH7, SystemIO, 0x15e0, 0x10) + Field(PMH7, ByteAcc, NoLock, Preserve) + { + Offset(0x0c), + PIDX, 8, + Offset(0x0e), + PDAT, 8, } - Method(_Q45, 0, NotSerialized) + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { - Notify(\_SB.DOCK, 3) + Offset (0x61), + DPWR, 1, } - Method(_Q50, 0, NotSerialized) + Method(_Q18, 0, NotSerialized) /* FN + F9 */ { + Debug = "_Q18" Notify(\_SB.DOCK, 3) } - Method(_Q58, 0, NotSerialized) - { - Notify(\_SB.DOCK, 0) - } - Method(_Q37, 0, NotSerialized) { + Debug = "_Q37" + Debug = "DPWR: " + Debug = DPWR + if (DPWR) { + Local0 = 2000 + Sleep (100) + \_SB.DOCK.G_ID = 0xffffffff + While((\_SB.DOCK.GGID () == 0x07) && Local0) + { + Sleep(1) + \_SB.DOCK.G_ID = 0xffffffff + Local0-- + } + Debug = "GGID: " + Debug = \_SB.DOCK.GGID () + \_SB.DOCK.DOID = 0xFFFFFFFF + If (((\_SB.DOCK.GDID () == 0x4C004D24) || (\_SB.DOCK.GDID () == 0x44004D24))) + { + Debug = "Notifying Dock 0" + \_SB.DOCK.DRST = 0 + Notify(\_SB.DOCK, 0) + } + Debug = "GDID: " + Debug = \_SB.DOCK.GDID () + } + } + + Method(_Q45, 0, NotSerialized) + { + Debug = "_Q45" + Notify(\_SB.DOCK, 3) + } + + Method(_Q50, 0, NotSerialized) /* Undock Button */ + { + Debug = "_Q50" + Local0 = \_SB.DOCK.GGID () + If (((Local0 == 0x00) || (Local0 == 0x01))) + { + \_SB.PCI0.LPCB.EC.LEDS = 0x88 + \_SB.PCI0.LPCB.EC.LEDS = 0xc9 + Notify (\_SB.DOCK, 0x03) // Eject Request + } + } + + Method(_Q58, 0, NotSerialized) + { + Debug = "_Q58" Notify(\_SB.DOCK, 0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/30397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa4a5a0272c6d3ec0b65871e5c1448d395bc74a8 Gerrit-Change-Number: 30397 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Autodisable functions based on devicetree
by Patrick Rudolph (Code Review) 23 Dec '18

23 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30244 ) Change subject: sb/intel/i82801gx: Autodisable functions based on devicetree ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/30244/12/src/southbridge/intel/i82801gx/i82… File src/southbridge/intel/i82801gx/i82801gx.c: https://review.coreboot.org/#/c/30244/12/src/southbridge/intel/i82801gx/i82… PS12, Line 25: switch (devfn) { why is internal lan missing ? -- To view, visit https://review.coreboot.org/c/coreboot/+/30244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Gerrit-Change-Number: 30244 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sun, 23 Dec 2018 15:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixed
by Tristan Corrick (Code Review) 23 Dec '18

23 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30273 ) Change subject: Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixed ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/30273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77 Gerrit-Change-Number: 30273 Gerrit-PatchSet: 6 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 23 Dec 2018 13:57:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/haswell: Add support for PCIe graphics
by Tristan Corrick (Code Review) 23 Dec '18

23 Dec '18

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30272 to look at the new patch set (#6). Change subject: nb/intel/haswell: Add support for PCIe graphics ...................................................................... nb/intel/haswell: Add support for PCIe graphics There are two different paths added for PEG link training. *The first path*: If it's okay for the IGD to be disabled, the link training is done in early romstage. The MRC will then set (and lock) GGC, and, if there is a device of VGA class present in a PEG slot, disable the IGD: Before the MRC: GGC = 0x0208, DEVEN = 0x00000039. After the MRC: GGC = 0x0003, DEVEN = 0x00000029. *The second path*: If the IGD needs to be kept enabled, the link training is done in ramstage. This is because the MRC will always disable the IGD if there is a device of VGA class in a PEG slot, but it can't see the device until link training is done. The second path can, unfortunately, lead to an increase in boot time, as the training needs to be complete before the PEG bus is scanned. When there are multiple PEG devices, the training occurs in parallel, limiting the impact on boot time. The worst case occurs when `CONFIG_ONBOARD_VGA_IS_PRIMARY` is set (which is not the default), the IGD is enabled, and there is an unpopulated PEG slot. This leads to the PEG training always hitting the timeout, which is 100 ms of wasted time. Only PEG2 is supported. An extra (unknown) training sequence is said to be needed for PEG3. The ACPI _PRT method is not yet generated, so legacy interrupt routing doesn't work for devices with multiple functions. Tested on an ASRock H81M-HDS. Using an x1 PCIe card in the PEG slot works fine. Using a Radeon HD 6450 graphics card also works under GNU/Linux, both using the display from the Radeon HD 6450, and when the IGD is used for display output and `DRI_PRIME=1` is set. Link training for the x1 PCIe card takes about 30 ms. For the Radeon HD 6450, it's about 15 ms. Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h A src/northbridge/intel/haswell/peg.c 4 files changed, 183 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30272/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/30272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Gerrit-Change-Number: 30272 Gerrit-PatchSet: 6 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP] nb/intel/haswell: Add support for PCIe graphics
by Tristan Corrick (Code Review) 23 Dec '18

23 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30272 ) Change subject: [WIP] nb/intel/haswell: Add support for PCIe graphics ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/30272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e Gerrit-Change-Number: 30272 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Dec 2018 12:53:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2018