coreboot-gerrit December 2018

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Change in ...coreboot[master]: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage
by Arthur Heymans (Code Review) 22 Dec '18

22 Dec '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30245 to look at the new patch set (#8). Change subject: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage ...................................................................... mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage With the i82801gx code automatically disabling devices ethernet NICs attached to the southbridge PCIe ports can now be disabled during the ramstage. Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/romstage.c M src/southbridge/intel/i82801gx/i82801gx.h 3 files changed, 28 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30245/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/30245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Gerrit-Change-Number: 30245 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/hatch: Add memory init setup for hatch
by Aamir Bohra (Code Review) 22 Dec '18

22 Dec '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30248 ) Change subject: mb/google/hatch: Add memory init setup for hatch ...................................................................... Patch Set 14: > Patch Set 13: > > please rebase this patch to get it merged ? Ok. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/30248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Gerrit-Change-Number: 30248 Gerrit-PatchSet: 14 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 13:29:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/wakeup.S: Use tabs instead of white spaces
by Tristan Corrick (Code Review) 22 Dec '18

22 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30379 ) Change subject: arch/x86/wakeup.S: Use tabs instead of white spaces ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Gerrit-Change-Number: 30379 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 13:15:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/arm/memmove.S: Use tabs instead of white spaces
by Tristan Corrick (Code Review) 22 Dec '18

22 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30378 ) Change subject: arch/arm/memmove.S: Use tabs instead of white spaces ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Gerrit-Change-Number: 30378 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 13:14:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: car/non-evict/exit_car.S: Use tabs instead of white spaces
by Tristan Corrick (Code Review) 22 Dec '18

22 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30376 ) Change subject: car/non-evict/exit_car.S: Use tabs instead of white spaces ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f Gerrit-Change-Number: 30376 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 13:14:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: x86/smm/smmhandler.S: Use tabs instead of white spaces
by Tristan Corrick (Code Review) 22 Dec '18

22 Dec '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30377 ) Change subject: x86/smm/smmhandler.S: Use tabs instead of white spaces ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/30377/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30377/2//COMMIT_MSG@7 PS2, Line 7: white spaces Tabs are white space, so I think it is more appropriate to just say "spaces" here. This also applies to the other patches in this series. -- To view, visit https://review.coreboot.org/c/coreboot/+/30377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce Gerrit-Change-Number: 30377 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 22 Dec 2018 13:13:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Fixes to initial hatch mainboard checkin
by Patrick Georgi (Code Review) 22 Dec '18

22 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30296 ) Change subject: mb/google/hatch: Fixes to initial hatch mainboard checkin ...................................................................... mb/google/hatch: Fixes to initial hatch mainboard checkin Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen(a)google.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h D src/mainboard/google/hatch/variants/hatch/overridetree.cb 6 files changed, 29 insertions(+), 106 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1c0208f..2400202 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -23,10 +23,14 @@ config CHROMEOS bool default y + select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH config DEVICETREE string @@ -68,10 +72,6 @@ int default 8 -config OVERRIDE_DEVICETREE - string - default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH - config TPM_TIS_ACPI_INTERRUPT int default 53 # GPE0_DW1_21 (GPP_C21) diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 36fba45..fa54148 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -29,29 +29,15 @@ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {-1, ACTIVE_HIGH, 0, "EC in RW"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static int cros_get_gpio_value(int type) +int get_write_protect_state(void) { - const struct cros_gpio *cros_gpios; - size_t i, num_gpios = 0; - - cros_gpios = variant_cros_gpios(&num_gpios); - - for (i = 0; i < num_gpios; i++) { - const struct cros_gpio *gpio = &cros_gpios[i]; - if (gpio->type == type) { - int state = gpio_get(gpio->gpio_num); - if (gpio->polarity == CROS_GPIO_ACTIVE_LOW) - return !state; - else - return state; - } - } - return 0; + return gpio_get(GPIO_PCH_WP); } void mainboard_chromeos_acpi_generate(void) @@ -63,18 +49,3 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } - -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - -int get_recovery_mode_switch(void) -{ - return cros_get_gpio_value(CROS_GPIO_REC); -} - -int get_lid_switch(void) -{ - return 1; -} diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 6631769..066cfbf 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -1,22 +1,20 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x1000000 { + SI_ALL@0x0 0x300000 { SI_DESC@0x0 0x1000 - SI_EC@0x1000 0x100000 - SI_GBE@0x101000 0x2000 - SI_ME@0x103000 0xefd000 + SI_ME@0x1000 0x2ff000 } SI_BIOS@0x1000000 0x1000000 { - RW_SECTION_A@0x0 0x280000 { + RW_SECTION_A@0x0 0x300000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x26ffc0 - RW_FWID_A@0x27ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x2effc0 + RW_FWID_A@0x2fffc0 0x40 } - RW_SECTION_B@0x280000 0x280000 { + RW_SECTION_B@0x300000 0x300000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x26ffc0 - RW_FWID_B@0x27ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x2effc0 + RW_FWID_B@0x2fffc0 0x40 } - RW_MISC@0x500000 0x30000 { + RW_MISC@0x600000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -29,17 +27,15 @@ RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - CONSOLE@0x530000 0x20000 - RW_LEGACY(CBFS)@0x550000 0x6b0000 - WP_RO@0xc00000 0x400000 { + RW_LEGACY(CBFS)@0x630000 0x5a0000 + WP_RO@0xbd0000 0x430000 { RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x3f0000 { + RO_SECTION@0x4000 0x42c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + COREBOOT(CBFS)@0xf0000 0x33c000 } } } diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 2517a58..69a0f37 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -29,6 +29,10 @@ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, INVERT), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), }; const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h index c9f8b4c..dc0ffee 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h @@ -18,4 +18,8 @@ #include <soc/gpio.h> +#define GPIO_EC_IN_RW GPP_C22 + +#define GPIO_PCH_WP GPP_C20 + #endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb deleted file mode 100644 index 88df092..0000000 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ /dev/null @@ -1,52 +0,0 @@ -chip soc/intel/cannonlake - device domain 0 on - device pci 00.0 off end # Host Bridge - device pci 02.0 off end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 off end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 off end # LPC/eSPI - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 off end # SMBus - device pci 1f.5 off end # PCH SPI - device pci 1f.6 off end # GbE - end -end -- To view, visit https://review.coreboot.org/c/coreboot/+/30296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Gerrit-Change-Number: 30296 Gerrit-PatchSet: 11 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: crossgcc: Update IASL and EXPAT versions
by HAOUAS Elyes (Code Review) 22 Dec '18

22 Dec '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30313 to look at the new patch set (#5). Change subject: crossgcc: Update IASL and EXPAT versions ...................................................................... crossgcc: Update IASL and EXPAT versions Update: * IASL to version 20181213 changes in this version: https://acpica.org/node/163 * EXPAT to version 2.2.6: changes in this version: https://github.com/libexpat/libexpat/blob/R_2_2_6/expat/Changes Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20181213_iasl.patch D util/crossgcc/sum/acpica-unix2-20181003.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20181213.tar.gz.cksum D util/crossgcc/sum/expat-2.2.5.tar.bz2.cksum A util/crossgcc/sum/expat-2.2.6.tar.bz2.cksum 6 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30313/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/30313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib67cf26497a0c2c2a364741675b13e4ce0190e41 Gerrit-Change-Number: 30313 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/wakeup.S: Use tabs instead of white spaces
by HAOUAS Elyes (Code Review) 22 Dec '18

22 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30379 Change subject: arch/x86/wakeup.S: Use tabs instead of white spaces ...................................................................... arch/x86/wakeup.S: Use tabs instead of white spaces Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/wakeup.S 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/30379/1 diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index aad72c2..ba502fe 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -29,29 +29,29 @@ .globl __wakeup __wakeup: #ifdef __x86_64__ - xor %rax,%rax - mov %ss, %ax - push %rax - mov %rsp, %rax - add $8, %rax - push %rax + xor %rax,%rax + mov %ss, %ax + push %rax + mov %rsp, %rax + add $8, %rax + push %rax pushfq - push $0x10 - lea 3(%rip), %rax - push %rax + push $0x10 + lea 3(%rip), %rax + push %rax iretq .code32 /* disable paging */ - mov %cr0, %eax - btc $31, %eax - mov %eax, %cr0 + mov %cr0, %eax + btc $31, %eax + mov %eax, %cr0 /* disable long mode */ - mov $0xC0000080, %ecx + mov $0xC0000080, %ecx rdmsr - btc $8, %eax + btc $8, %eax wrmsr #endif /* First prepare the jmp to the resume vector */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Gerrit-Change-Number: 30379 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/arm/memmove.S: Use tabs instead of white spaces
by HAOUAS Elyes (Code Review) 22 Dec '18

22 Dec '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30378 Change subject: arch/arm/memmove.S: Use tabs instead of white spaces ...................................................................... arch/arm/memmove.S: Use tabs instead of white spaces Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/memmove.S 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/30378/1 diff --git a/src/arch/arm/memmove.S b/src/arch/arm/memmove.S index 3114c7e..f4da9e8 100644 --- a/src/arch/arm/memmove.S +++ b/src/arch/arm/memmove.S @@ -149,26 +149,26 @@ PLD( pld [r1, #-96] ) 12: PLD( pld [r1, #-128] ) -13: ldmdb r1!, {r7, r8, r9, ip} - mov lr, r3, push #\push - subs r2, r2, #32 - ldmdb r1!, {r3, r4, r5, r6} - orr lr, lr, ip, pull #\pull - mov ip, ip, push #\push - orr ip, ip, r9, pull #\pull - mov r9, r9, push #\push - orr r9, r9, r8, pull #\pull - mov r8, r8, push #\push - orr r8, r8, r7, pull #\pull - mov r7, r7, push #\push - orr r7, r7, r6, pull #\pull - mov r6, r6, push #\push - orr r6, r6, r5, pull #\pull - mov r5, r5, push #\push - orr r5, r5, r4, pull #\pull - mov r4, r4, push #\push - orr r4, r4, r3, pull #\pull - stmdb r0!, {r4 - r9, ip, lr} +13: ldmdb r1!, {r7, r8, r9, ip} + mov lr, r3, push #\push + subs r2, r2, #32 + ldmdb r1!, {r3, r4, r5, r6} + orr lr, lr, ip, pull #\pull + mov ip, ip, push #\push + orr ip, ip, r9, pull #\pull + mov r9, r9, push #\push + orr r9, r9, r8, pull #\pull + mov r8, r8, push #\push + orr r8, r8, r7, pull #\pull + mov r7, r7, push #\push + orr r7, r7, r6, pull #\pull + mov r6, r6, push #\push + orr r6, r6, r5, pull #\pull + mov r5, r5, push #\push + orr r5, r5, r4, pull #\pull + mov r4, r4, push #\push + orr r4, r4, r3, pull #\pull + stmdb r0!, {r4 - r9, ip, lr} bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) @@ -178,7 +178,7 @@ 14: ands ip, r2, #28 beq 16f -15: mov lr, r3, push #\push +15: mov lr, r3, push #\push ldr r3, [r1, #-4]! subs ip, ip, #4 orr lr, lr, r3, pull #\pull -- To view, visit https://review.coreboot.org/c/coreboot/+/30378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Gerrit-Change-Number: 30378 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit December 2018