coreboot-gerrit January 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common: Add S3 resume functions to wrapper
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22730 ) Change subject: soc/amd/common: Add S3 resume functions to wrapper ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66849/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21441/ : SUCCESS -- To view, visit https://review.coreboot.org/22730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01 Gerrit-Change-Number: 22730 Gerrit-PatchSet: 9 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:28:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Move TValid and SmmLock to end of POST
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23437 ) Change subject: amd/stoneyridge: Move TValid and SmmLock to end of POST ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66844/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21439/ : SUCCESS -- To view, visit https://review.coreboot.org/23437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab Gerrit-Change-Number: 23437 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:26:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common: Add S3 supporting functions
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22727 ) Change subject: soc/amd/common: Add S3 supporting functions ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66846/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21437/ : SUCCESS -- To view, visit https://review.coreboot.org/22727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63 Gerrit-Change-Number: 22727 Gerrit-PatchSet: 9 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:20:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: commonlib: Add AGESA S3 resume defines
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23439 ) Change subject: commonlib: Add AGESA S3 resume defines ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66845/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21438/ : SUCCESS -- To view, visit https://review.coreboot.org/23439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b50e76a0c49c1f317f9294c5f95735e7aa5d95c Gerrit-Change-Number: 23439 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:19:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: lib/stage_cache: Add save/get raw storage
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23518 Change subject: lib/stage_cache: Add save/get raw storage ...................................................................... lib/stage_cache: Add save/get raw storage Leverage the stage_cache mechanism to store a non-specific type of data. This is not interesting when the location for the cache is in cbmem. However it will be more useful when an external location is used, e.g. when the cache is in TSEG, locked from user modification. Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/include/stage_cache.h M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c 4 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23518/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 9a66246..3529fef 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -61,6 +61,7 @@ #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 +#define CBMEM_ID_STAGEx_RAW 0x57a9e200 #define CBMEM_ID_STORAGE_DATA 0x53746f72 #define CBMEM_ID_TCPA_LOG 0x54435041 #define CBMEM_ID_TIMESTAMP 0x54494d45 diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 08312ff..f276380 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -24,10 +24,15 @@ STAGE_RAMSTAGE, STAGE_REFCODE, STAGE_POSTCAR, + STAGE_S3_DATA, }; /* Cache the loaded stage provided according to the parameters. */ void stage_cache_add(int stage_id, const struct prog *stage); +/* Cache non-specific data or code. */ +void stage_cache_add_raw(int stage_id, const void *base, const size_t size); +/* Get a pointer to cached raw data and its size. */ +void stage_cache_get_raw(int stage_id, void **base, size_t *size); /* Load the cached stage at given location returning the stage entry point. */ void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index cc4832f..299cb00 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -17,6 +17,7 @@ #include <cbmem.h> #include <stage_cache.h> #include <string.h> +#include <console/console.h> /* Stage cache uses cbmem. */ void stage_cache_add(int stage_id, const struct prog *stage) @@ -44,6 +45,35 @@ memcpy(c, prog_start(stage), prog_size(stage)); } +void stage_cache_add_raw(int stage_id, const void *base, const size_t size) +{ + void *c; + + c = cbmem_add(CBMEM_ID_STAGEx_RAW + stage_id, size); + if (c == NULL) { + printk(BIOS_DEBUG, "Error: Can't add %x raw data to cbmem\n", + CBMEM_ID_STAGEx_RAW + stage_id); + return; + } + + memcpy(c, base, size); +} + +void stage_cache_get_raw(int stage_id, void **base, size_t *size) +{ + const struct cbmem_entry *e; + + e = cbmem_entry_find(CBMEM_ID_STAGEx_RAW + stage_id); + if (e == NULL) { + printk(BIOS_ERR, "Error: Can't find raw %x data in cbmem\n", + CBMEM_ID_STAGEx_RAW + stage_id); + return; + } + + *base = cbmem_entry_start(e); + *size = cbmem_entry_size(e); +} + void stage_cache_load_stage(int stage_id, struct prog *stage) { struct stage_cache *meta; diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index cea9f52..ab78347 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -93,6 +93,47 @@ memcpy(c, prog_start(stage), prog_size(stage)); } +void stage_cache_add_raw(int stage_id, const void *base, const size_t size) +{ + struct imd *imd; + const struct imd_entry *e; + void *c; + + imd = imd_get(); + e = imd_entry_add(imd, CBMEM_ID_STAGEx_RAW + stage_id, size); + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't add %x raw data to imd\n", + CBMEM_ID_STAGEx_RAW + stage_id); + return; + } + + c = imd_entry_at(imd, e); + if (c == NULL) { + printk(BIOS_DEBUG, "Error: Can't get %x raw entry in imd\n", + CBMEM_ID_STAGEx_RAW + stage_id); + return; + } + + memcpy(c, base, size); +} + +void stage_cache_get_raw(int stage_id, void **base, size_t *size) +{ + struct imd *imd; + const struct imd_entry *e; + + imd = imd_get(); + e = imd_entry_find(imd, CBMEM_ID_STAGEx_RAW + stage_id); + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't find %x raw data to imd\n", + CBMEM_ID_STAGEx_RAW + stage_id); + return; + } + + *base = imd_entry_at(imd, e); + *size = imd_entry_size(imd, e); +} + void stage_cache_load_stage(int stage_id, struct prog *stage) { struct imd *imd; -- To view, visit https://review.coreboot.org/23518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f Gerrit-Change-Number: 23518 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Put stage cache into TSEG
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23519 Change subject: amd/stoneyridge: Put stage cache into TSEG ...................................................................... amd/stoneyridge: Put stage cache into TSEG Add a function to allow an external region to be located in TSEG. Select the option to use memory outside of cbmem. Increase the size reserved in TSEG. Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/ramtop.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23519/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 148ca3f..7975523 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -55,6 +55,7 @@ select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select RELOCATABLE_MODULES + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER @@ -295,7 +296,7 @@ config SMM_RESERVED_SIZE hex - default 0x100000 + default 0x140000 config ACPI_CPU_STRING string diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index e676465..ca7511b 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -21,6 +21,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cbmem.h> +#include <stage_cache.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -56,6 +57,15 @@ return CONFIG_SMM_TSEG_SIZE; } +void stage_cache_external_region(void **base, size_t *size) +{ + if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { + printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); + *base = NULL; + *size = 0; + } +} + void smm_region_info(void **start, size_t *size) { *start = (void *)smm_region_start(); -- To view, visit https://review.coreboot.org/23519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66 Gerrit-Change-Number: 23519 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/soc/common: Remove cbmem subregions in heap
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23516 Change subject: amd/soc/common: Remove cbmem subregions in heap ...................................................................... amd/soc/common: Remove cbmem subregions in heap Revert most of 4f3f47b "amd/common: Define regions in cbmem". This puts the management of the heap space back to its traditional methodology. Subsequent patches that were to have used these subregions have been reworked. Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h D src/soc/amd/common/block/include/amdblocks/s3_resume.h M src/soc/amd/common/block/pi/heapmanager.c 3 files changed, 1 insertion(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/23516/1 diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 8a9474e..e061c63 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -18,18 +18,10 @@ #define __CALLOUTS_AMD_AGESA_H__ #include <amdblocks/agesawrapper.h> -#include <amdblocks/s3_resume.h> #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000 -struct cbmem_usage { - uint8_t heap_base[BIOS_HEAP_SIZE]; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - uint8_t s3_vol_data[S3_VOLATILE_SIZE]; -#endif -}; - typedef struct _BIOS_HEAP_MANAGER { UINT32 StartOfAllocatedNodes; UINT32 StartOfFreedNodes; diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h deleted file mode 100644 index 567b0a8..0000000 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AMD_S3_RESUME_H__ -#define __AMD_S3_RESUME_H__ - -#define S3_VOLATILE_SIZE 0x6000 - -#endif /* __AMD_S3_RESUME_H__ */ diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index 6b47ec3..79c8403 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -21,10 +21,7 @@ void *agesa_heap_base(void) { - struct cbmem_usage *heap; - heap = (struct cbmem_usage *)cbmem_add(CBMEM_ID_RESUME_SCRATCH, - sizeof(struct cbmem_usage)); - return &heap->heap_base; + return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE); } static void EmptyHeap(int unused) -- To view, visit https://review.coreboot.org/23516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912 Gerrit-Change-Number: 23516 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: lib/stage_cache: Add debug messages for failures
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/23517 Change subject: lib/stage_cache: Add debug messages for failures ...................................................................... lib/stage_cache: Add debug messages for failures Communicate additional status to the console when the save and load functions do not function as expected. The most likely scenario for an error is when using a cache that is external to cbmem, and restricted in size. Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c 2 files changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23517/1 diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 2947972..cc4832f 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -25,15 +25,21 @@ void *c; meta = cbmem_add(CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); - if (meta == NULL) + if (meta == NULL) { + printk(BIOS_ERR, "Error: Can't add %x metadata to cbmem\n", + CBMEM_ID_STAGEx_META + stage_id); return; + } meta->load_addr = (uintptr_t)prog_start(stage); meta->entry_addr = (uintptr_t)prog_entry(stage); meta->arg = (uintptr_t)prog_entry_arg(stage); c = cbmem_add(CBMEM_ID_STAGEx_CACHE + stage_id, prog_size(stage)); - if (c == NULL) + if (c == NULL) { + printk(BIOS_ERR, "Error: Can't add stage_cache %x to cbmem\n", + CBMEM_ID_STAGEx_CACHE + stage_id); return; + } memcpy(c, prog_start(stage), prog_size(stage)); } @@ -49,13 +55,19 @@ prog_set_entry(stage, NULL, NULL); meta = cbmem_find(CBMEM_ID_STAGEx_META + stage_id); - if (meta == NULL) + if (meta == NULL) { + printk(BIOS_ERR, "Error: Can't find %x metadata in cbmem\n", + CBMEM_ID_STAGEx_META + stage_id); return; + } e = cbmem_entry_find(CBMEM_ID_STAGEx_CACHE + stage_id); - if (e == NULL) + if (e == NULL) { + printk(BIOS_ERR, "Error: Can't find stage_cache %x in cbmem\n", + CBMEM_ID_STAGEx_CACHE + stage_id); return; + } c = cbmem_entry_start(e); size = cbmem_entry_size(e); diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2a99188..cea9f52 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -68,8 +68,11 @@ imd = imd_get(); e = imd_entry_add(imd, CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); - if (e == NULL) + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't add %x metadata to imd\n", + CBMEM_ID_STAGEx_META + stage_id); return; + } meta = imd_entry_at(imd, e); @@ -79,8 +82,11 @@ e = imd_entry_add(imd, CBMEM_ID_STAGEx_CACHE + stage_id, prog_size(stage)); - if (e == NULL) + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't add stage_cache %x to imd\n", + CBMEM_ID_STAGEx_CACHE + stage_id); return; + } c = imd_entry_at(imd, e); @@ -97,15 +103,21 @@ imd = imd_get(); e = imd_entry_find(imd, CBMEM_ID_STAGEx_META + stage_id); - if (e == NULL) + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't find %x metadata in imd\n", + CBMEM_ID_STAGEx_META + stage_id); return; + } meta = imd_entry_at(imd, e); e = imd_entry_find(imd, CBMEM_ID_STAGEx_CACHE + stage_id); - if (e == NULL) + if (e == NULL) { + printk(BIOS_DEBUG, "Error: Can't find stage_cache %x in imd\n", + CBMEM_ID_STAGEx_CACHE + stage_id); return; + } c = imd_entry_at(imd, e); size = imd_entry_size(imd, e); -- To view, visit https://review.coreboot.org/23517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Gerrit-Change-Number: 23517 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: payloads: Add LinuxBoot payload in u-root mode
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23071 ) Change subject: payloads: Add LinuxBoot payload in u-root mode ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/21436/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/66843/ : SUCCESS -- To view, visit https://review.coreboot.org/23071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659 Gerrit-Change-Number: 23071 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chris K <c(a)chrisko.ch> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich Gerrit-Comment-Date: Wed, 31 Jan 2018 18:38:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Add grunt cr50 support
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23514 ) Change subject: mb/google/kahlee: Add grunt cr50 support ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/66842/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21435/ : SUCCESS -- To view, visit https://review.coreboot.org/23514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Gerrit-Change-Number: 23514 Gerrit-PatchSet: 4 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 16:34:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit January 2018