coreboot-gerrit January 2018

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Change in coreboot[master]: util/inteltool: Add Pentium 4 model f6x.
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23521 ) Change subject: util/inteltool: Add Pentium 4 model f6x. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66863/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21456/ : SUCCESS -- To view, visit https://review.coreboot.org/23521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Gerrit-Change-Number: 23521 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 20:37:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: lib/stage_cache: Add debug messages for failures
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23517 to look at the new patch set (#2). Change subject: lib/stage_cache: Add debug messages for failures ...................................................................... lib/stage_cache: Add debug messages for failures Communicate additional status to the console when the save and load functions do not function as expected. The most likely scenario for an error is when using a cache that is external to cbmem, and restricted in size. Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/lib/cbmem_stage_cache.c M src/lib/ext_stage_cache.c 2 files changed, 33 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/23517/2 -- To view, visit https://review.coreboot.org/23517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Gerrit-Change-Number: 23517 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/stoneyridge: Put stage cache into TSEG
by Marshall Dawson (Code Review) 31 Jan '18

31 Jan '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/23519 to look at the new patch set (#2). Change subject: amd/stoneyridge: Put stage cache into TSEG ...................................................................... amd/stoneyridge: Put stage cache into TSEG Add a function to allow an external region to be located in TSEG. Select the option to use memory outside of cbmem. Increase the size reserved in TSEG. Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/ramtop.c 2 files changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23519/2 -- To view, visit https://review.coreboot.org/23519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66 Gerrit-Change-Number: 23519 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/inteltool: Add Pentium 4 model f6x.
by Elyes HAOUAS (Code Review) 31 Jan '18

31 Jan '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23521 Change subject: util/inteltool: Add Pentium 4 model f6x. ...................................................................... util/inteltool: Add Pentium 4 model f6x. Tested on Pentium 4, CPUID = 0F65. Board: NEC 945G-M4 Command: "modprobe msr && ./inteltool -M" Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/inteltool/cpu.c 1 file changed, 256 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23521/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 360b86b..3bce3b8 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -868,6 +868,261 @@ }; + + /* + * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual + * September 2016 + */ + static const msr_entry_t modelf6x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x002b, "MSR_EBC_SOFT_POWERON" }, + { 0x002c, "MSR_EBC_FREQUENCY_ID" }, +// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01a1, "MSR_PLATFORM_BRV" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + { 0x0302, "MSR_BPU_COUNTER2" }, + { 0x0303, "MSR_BPU_COUNTER3" }, + { 0x0304, "MSR_MS_COUNTER0" }, + { 0x0305, "MSR_MS_COUNTER1" }, + { 0x0306, "MSR_MS_COUNTER2" }, + { 0x0307, "MSR_MS_COUNTER3" }, + { 0x0308, "MSR_FLAME_COUNTER0" }, + { 0x0309, "MSR_FLAME_COUNTER1" }, + { 0x030a, "MSR_FLAME_COUNTER2" }, + { 0x030b, "MSR_FLAME_COUNTER3" }, + { 0x030c, "MSR_IQ_COUNTER0" }, + { 0x030d, "MSR_IQ_COUNTER1" }, + { 0x030e, "MSR_IQ_COUNTER2" }, + { 0x030f, "MSR_IQ_COUNTER3" }, + { 0x0310, "MSR_IQ_COUNTER4" }, + { 0x0311, "MSR_IQ_COUNTER5" }, + { 0x0360, "MSR_BPU_CCCR0" }, + { 0x0361, "MSR_BPU_CCCR1" }, + { 0x0362, "MSR_BPU_CCCR2" }, + { 0x0363, "MSR_BPU_CCCR3" }, + { 0x0364, "MSR_MS_CCCR0" }, + { 0x0365, "MSR_MS_CCCR1" }, + { 0x0366, "MSR_MS_CCCR2" }, + { 0x0367, "MSR_MS_CCCR3" }, + { 0x0368, "MSR_FLAME_CCCR0" }, + { 0x0369, "MSR_FLAME_CCCR1" }, + { 0x036A, "MSR_FLAME_CCCR2" }, + { 0x036B, "MSR_FLAME_CCCR3" }, + { 0x036C, "MSR_IQ_CCCR0" }, + { 0x036D, "MSR_IQ_CCCR1" }, + { 0x036E, "MSR_IQ_CCCR2" }, + { 0x036F, "MSR_IQ_CCCR3" }, + { 0x0370, "MSR_IQ_CCCR4" }, + { 0x0371, "MSR_IQ_CCCR5" }, + { 0x03A0, "MSR_BSU_ESCR0" }, + { 0x03A1, "MSR_BSU_ESCR1" }, + { 0x03A2, "MSR_FSB_ESCR0" }, + { 0x03A3, "MSR_FSB_ESCR1" }, + { 0x03A4, "MSR_FIRM_ESCR0" }, + { 0x03A5, "MSR_FIRM_ESCR1" }, + { 0x03A6, "MSR_FLAME_ESCR0" }, + { 0x03A7, "MSR_FLAME_ESCR1" }, + { 0x03A8, "MSR_DAC_ESCR0" }, + { 0x03A9, "MSR_DAC_ESCR1" }, + { 0x03AA, "MSR_MOB_ESCR0" }, + { 0x03AB, "MSR_MOB_ESCR1" }, + { 0x03AC, "MSR_PMH_ESCR0" }, + { 0x03AD, "MSR_PMH_ESCR1" }, + { 0x03AE, "MSR_SAAT_ESCR0" }, + { 0x03AF, "MSR_SAAT_ESCR1" }, + { 0x03B0, "MSR_U2L_ESCR0" }, + { 0x03B1, "MSR_U2L_ESCR1" }, + { 0x03B2, "MSR_BPU_ESCR0" }, + { 0x03B3, "MSR_BPU_ESCR1" }, + { 0x03B4, "MSR_IS_ESCR0" }, + { 0x03B5, "MSR_IS_ESCR1" }, + { 0x03B6, "MSR_ITLB_ESCR0" }, + { 0x03B7, "MSR_ITLB_ESCR1" }, + { 0x03B8, "MSR_CRU_ESCR0" }, + { 0x03B9, "MSR_CRU_ESCR1" }, + { 0x03BA, "MSR_IQ_ESCR0" }, + { 0x03BB, "MSR_IQ_ESCR1" }, + { 0x03BC, "MSR_RAT_ESCR0" }, + { 0x03BD, "MSR_RAT_ESCR1" }, + { 0x03BE, "MSR_SSU_ESCR0" }, + { 0x03C0, "MSR_MS_ESCR0" }, + { 0x03C1, "MSR_MS_ESCR1" }, + { 0x03C2, "MSR_TBPU_ESCR0" }, + { 0x03C3, "MSR_TBPU_ESCR1" }, + { 0x03C4, "MSR_TC_ESCR0" }, + { 0x03C5, "MSR_TC_ESCR1" }, + { 0x03C8, "MSR_IX_ESCR0" }, + { 0x03C9, "MSR_IX_ESCR1" }, + { 0x03CA, "MSR_ALF_ESCR0" }, + { 0x03CB, "MSR_ALF_ESCR1" }, + { 0x03CC, "MSR_CRU_ESCR2" }, + { 0x03CD, "MSR_CRU_ESCR3" }, + { 0x03E0, "MSR_CRU_ESCR4" }, + { 0x03E1, "MSR_CRU_ESCR5" }, + { 0x03F0, "MSR_TC_PRECISE_EVENT" }, + { 0x03F1, "MSR_PEBS_ENABLE" }, + { 0x03F2, "MSR_PEBS_MATRIX_VERT" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0407, "IA32_MC1_MISC" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + { 0x040b, "IA32_MC2_MISC" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x040f, "IA32_MC3_MISC" }, + { 0x0410, "IA32_MC4_CTL" }, + { 0x0411, "IA32_MC4_STATUS" }, + { 0x0412, "IA32_MC4_ADDR" }, + { 0x0413, "IA32_MC4_MISC" }, + }; + + static const msr_entry_t modelf6x_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x009b, "IA32_SMM_MONITOR_CTL" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017b, "IA32_MCG_CTL" }, + { 0x0180, "MSR_MCG_RAX" }, + { 0x0181, "MSR_MCG_RBX" }, + { 0x0182, "MSR_MCG_RCX" }, + { 0x0183, "MSR_MCG_RDX" }, + { 0x0184, "MSR_MCG_RSI" }, + { 0x0185, "MSR_MCG_RDI" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x018a, "MSR_MCG_MISC" }, +// 0x018B - 0x018F : MSR_MCG_RESERVED1 - MSR_MCG_RESERVED5 + { 0x0190, "MSR_MCG_R8" }, + { 0x0191, "MSR_MCG_R9" }, + { 0x0192, "MSR_MCG_R10" }, + { 0x0193, "MSR_MCG_R11" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0195, "MSR_MCG_R13" }, + { 0x0196, "MSR_MCG_R14" }, + { 0x0197, "MSR_MCG_R15" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01d7, "MSR_LER_FROM_LIP" }, + { 0x01d8, "MSR_LER_TO_LIP" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01da, "MSR_LASTBRANCH_TOS" }, + { 0x01db, "MSR_LASTBRANCH_0" }, + { 0x01dc, "MSR_LASTBRANCH_1" }, + { 0x01dd, "MSR_LASTBRANCH_2" }, + { 0x01de, "MSR_LASTBRANCH_3" }, + { 0x0277, "IA32_PAT" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x0600, "IA32_DS_AREA" }, + { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, + { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, + { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, + { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, + { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, + { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, + { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, + { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, + { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, + { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, + { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, + { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, + { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, + { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, + { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, + { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, + { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, + /* Intel Xeon processor 7100 with L3 */ + { 0x107CC, "MSR_EMON_L3_CTR_CTL0" }, + { 0x107CD, "MSR_EMON_L3_CTR_CTL1" }, + { 0x107CE, "MSR_EMON_L3_CTR_CTL2" }, + { 0x107CF, "MSR_EMON_L3_CTR_CTL3" }, + { 0x107D0, "MSR_EMON_L3_CTR_CTL4" }, + { 0x107D1, "MSR_EMON_L3_CTR_CTL5" }, + { 0x107D2, "MSR_EMON_L3_CTR_CTL6" }, + { 0x107D3, "MSR_EMON_L3_CTR_CTL7" }, + }; + + /* Atom N455 * * This should apply to the following processors: @@ -1316,6 +1571,7 @@ { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, + { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, -- To view, visit https://review.coreboot.org/23521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c Gerrit-Change-Number: 23521 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/kahlee: Add grunt cr50 support
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23514 ) Change subject: mb/google/kahlee: Add grunt cr50 support ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66862/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21454/ : SUCCESS -- To view, visit https://review.coreboot.org/23514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Gerrit-Change-Number: 23514 Gerrit-PatchSet: 5 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 20:19:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Add grunt trackpad in devicetree
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23508 ) Change subject: mb/google/kahlee: Add grunt trackpad in devicetree ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66861/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21455/ : SUCCESS -- To view, visit https://review.coreboot.org/23508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50 Gerrit-Change-Number: 23508 Gerrit-PatchSet: 3 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 20:16:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: Fix grunt I2C rise/fall times
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23520 ) Change subject: mb/google/kahlee: Fix grunt I2C rise/fall times ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66860/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21453/ : SUCCESS -- To view, visit https://review.coreboot.org/23520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Gerrit-Change-Number: 23520 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 20:16:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Fix grunt I2C rise/fall times
by Justin TerAvest (Code Review) 31 Jan '18

31 Jan '18

Justin TerAvest has uploaded this change for review. ( https://review.coreboot.org/23520 Change subject: mb/google/kahlee: Fix grunt I2C rise/fall times ...................................................................... mb/google/kahlee: Fix grunt I2C rise/fall times I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Signed-off-by: Justin TerAvest <teravest(a)chromium.org> --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/23520/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 9665a78..7ffc0ac 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -21,11 +21,11 @@ register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "128 * MiB" - # TODO(teravest): Fix speeds here. + # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 95, + .fall_time_ns = 3, }" # Enable I2C1 for H1 at 400kHz @@ -36,18 +36,18 @@ .fall_time_ns = 4, }" - # TODO(teravest): Fix speeds here. + # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 117, + .fall_time_ns = 113, }" - # TODO(teravest): Fix speeds here. + # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, + .rise_time_ns = 82, + .fall_time_ns = 67, }" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/23520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Gerrit-Change-Number: 23520 Gerrit-PatchSet: 1 Gerrit-Owner: Justin TerAvest <teravest(a)chromium.org>

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Change in coreboot[master]: lib/stage_cache: Add debug messages for failures
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23517 ) Change subject: lib/stage_cache: Add debug messages for failures ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/66857/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/21450/ : SUCCESS -- To view, visit https://review.coreboot.org/23517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c Gerrit-Change-Number: 23517 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:59:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/soc/common: Remove cbmem subregions in heap
by build bot (Jenkins) (Code Review) 31 Jan '18

31 Jan '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23516 ) Change subject: amd/soc/common: Remove cbmem subregions in heap ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/66856/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/21449/ : SUCCESS -- To view, visit https://review.coreboot.org/23516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912 Gerrit-Change-Number: 23516 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Jan 2018 19:58:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit January 2018