coreboot-gerrit September 2017

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Change in coreboot[master]: arch/riscv: Use a separate trap stack
by Jonathan Neuschäfer (Code Review) 26 Sep '17

26 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21689 Change subject: arch/riscv: Use a separate trap stack ...................................................................... arch/riscv: Use a separate trap stack This is the lazy solution, as explained in the comment, but it works for now. Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/trap_util.S 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/21689/1 diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index ae32379..7af4fe1 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -128,10 +128,14 @@ .Lsmp_hang: bnez sp, .Lsmp_hang - # TODO: Use the old stack pointer (plus an offset) for exceptions in machine - # mode, to avoid overwriting stack data. - la sp, _estack - addi sp,sp,-MENTRY_FRAME_SIZE + # Use a different stack than in the main context, to to avoid overwriting + # stack data. + # TODO: Maybe use the old stack pointer (plus an offset) instead. But only if + # the previous mode was M, because it would be a very bad idea to use a stack + # pointer provided by unprivileged code! + la sp, _estack + addi sp, sp, -2048 # 2 KiB is half of the stack space + addi sp, sp, -MENTRY_FRAME_SIZE save_tf move a0,sp -- To view, visit https://review.coreboot.org/21689 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d Gerrit-Change-Number: 21689 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: arch/riscv: mprv_read_*: Mark result as earlyclobber
by Jonathan Neuschäfer (Code Review) 26 Sep '17

26 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21688 Change subject: arch/riscv: mprv_read_*: Mark result as earlyclobber ...................................................................... arch/riscv: mprv_read_*: Mark result as earlyclobber This fixes a case of mstatus corruption, where GCC generated code that used the same register for the mprv bit and the result. GCC inline assembly register modifiers are documented here: https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/include/vm.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/21688/1 diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index a65aba9..af90e14 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -73,7 +73,7 @@ "csrs mstatus, %1\n" \ STRINGIFY(insn) " %0, 0(%2)\n" \ "csrc mstatus, %1\n" \ - : "=r"(value) : "r"(mprv), "r"(p) : "memory" \ + : "=&r"(value) : "r"(mprv), "r"(p) : "memory" \ ); \ return value; \ } -- To view, visit https://review.coreboot.org/21688 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3 Gerrit-Change-Number: 21688 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: arch/riscv: gettimer: Don't use the config string
by Jonathan Neuschäfer (Code Review) 26 Sep '17

26 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21687 Change subject: arch/riscv: gettimer: Don't use the config string ...................................................................... arch/riscv: gettimer: Don't use the config string Accessing the config string doesn't work anymore on current versions of spike. Thus return dummy pointers until we have a better solution. Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/trap_handler.c 1 file changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/21687/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ca4954f..54cd7e7 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -125,17 +125,19 @@ static void gettimer(void) { - query_result res; - const char *config; + /* + * FIXME: This hard-coded value (currently) works on spike, but we + * should really read it from the device tree. + */ + uintptr_t clint = 0x02000000; - config = configstring(); - query_rtc(config, (uintptr_t *)&time); + time = (void *)(clint + 0xbff8); + timecmp = (void *)(clint + 0x4000); + if (!time) die("Got timer interrupt but found no timer."); - res = query_config_string(config, "core{0{0{timecmp"); - timecmp = (void *)get_uint(res); if (!timecmp) - die("Got a timer interrupt but found no timecmp."); + die("Got timer interrupt but found no timecmp."); } static void interrupt_handler(trapframe *tf) -- To view, visit https://review.coreboot.org/21687 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1 Gerrit-Change-Number: 21687 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: [HACK] arch/riscv: build the code without RVC
by Jonathan Neuschäfer (Code Review) 26 Sep '17

26 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21686 Change subject: [HACK] arch/riscv: build the code without RVC ...................................................................... [HACK] arch/riscv: build the code without RVC RVC (the RISC-V Compressed extension) cases problems for handle_misaligned_{load,store}, but I feel there should be a better solution than simply hard-coding the architecture variant that I'm currently testing against. IOW: Do not merge, for now. Change-Id: Iea8fc6657c196f8580a51f0cb75d5532254bd7c2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/21686/1 diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index c68fd1e..47dbe7a 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -15,9 +15,9 @@ ## ################################################################################ -riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany +riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=rv64imafd -riscv_asm_flags = +riscv_asm_flags = -march=rv64imafd ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) check-ramstage-overlap-regions += stack -- To view, visit https://review.coreboot.org/21686 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea8fc6657c196f8580a51f0cb75d5532254bd7c2 Gerrit-Change-Number: 21686 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: util/crossgcc: Add bootstrap-only mode
by Jonathan Neuschäfer (Code Review) 25 Sep '17

25 Sep '17

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/21683 ) Change subject: util/crossgcc: Add bootstrap-only mode ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21683 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I089b51d1b898d4cf530845ba51283997fd229451 Gerrit-Change-Number: 21683 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 23:00:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Refactor GPIO functions
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21684 ) Change subject: amd/stoneyridge: Refactor GPIO functions ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61078/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16250/ : SUCCESS -- To view, visit https://review.coreboot.org/21684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Gerrit-Change-Number: 21684 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 21:40:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Fix GPIO ASL
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21614 ) Change subject: google/kahlee: Fix GPIO ASL ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61077/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16249/ : SUCCESS -- To view, visit https://review.coreboot.org/21614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Gerrit-Change-Number: 21614 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 21:39:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Refactor GPIO functions
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21684 ) Change subject: amd/stoneyridge: Refactor GPIO functions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61076/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16248/ : SUCCESS -- To view, visit https://review.coreboot.org/21684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Gerrit-Change-Number: 21684 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 21:27:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Fix GPIO ASL
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21614 ) Change subject: google/kahlee: Fix GPIO ASL ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61075/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16247/ : SUCCESS -- To view, visit https://review.coreboot.org/21614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Gerrit-Change-Number: 21614 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 21:25:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Refactor GPIO functions
by Marc Jones (Code Review) 25 Sep '17

25 Sep '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21684 Change subject: amd/stoneyridge: Refactor GPIO functions ...................................................................... amd/stoneyridge: Refactor GPIO functions Refactor the GPIO functions to use GPIO numbers. This is more consitent with other GPIO code in coreboot. BUG=b:66462235 BRANCH=none TEST=Build and boot Kahlee Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/chromeos.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/gpio.h 3 files changed, 123 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/21684/1 diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 156614b..a8b1f34 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -17,7 +17,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <boot/coreboot_tables.h> -#include <console/console.h> #include <gpio.h> /* SPI Write protect */ diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 7e19d99..86655fc 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -16,26 +16,40 @@ */ #include <arch/io.h> +#include <console/console.h> #include <gpio.h> #include <soc/gpio.h> -/* The following functions must be implemented by SoC/board code. */ +static uintptr_t gpio_get_address(gpio_t gpio_num) +{ + uintptr_t gpio_address; + + if (gpio_num < 64) + gpio_address = GPIO_BANK0_CONTROL(gpio_num); + else if (gpio_num < 128) + gpio_address = GPIO_BANK1_CONTROL(gpio_num); + else + gpio_address = GPIO_BANK2_CONTROL(gpio_num); + + return gpio_address; +} int gpio_get(gpio_t gpio_num) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); return !!(reg & GPIO_PIN_STS); } - void gpio_set(gpio_t gpio_num, int value) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); reg &= ~GPIO_OUTPUT_MASK; reg |= !!value << GPIO_OUTPUT_SHIFT; write32((void *)(uintptr_t)gpio_num, reg); @@ -44,8 +58,9 @@ void gpio_input_pulldown(gpio_t gpio_num) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); reg &= ~GPIO_PULLUP_ENABLE; reg |= GPIO_PULLDOWN_ENABLE; write32((void *)(uintptr_t)gpio_num, reg); @@ -54,8 +69,9 @@ void gpio_input_pullup(gpio_t gpio_num) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); reg &= ~GPIO_PULLDOWN_ENABLE; reg |= GPIO_PULLUP_ENABLE; write32((void *)(uintptr_t)gpio_num, reg); @@ -64,8 +80,9 @@ void gpio_input(gpio_t gpio_num) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); reg &= ~GPIO_OUTPUT_ENABLE; write32((void *)(uintptr_t)gpio_num, reg); } @@ -73,8 +90,9 @@ void gpio_output(gpio_t gpio_num, int value) { uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); - reg = read32((void *)(uintptr_t)gpio_num); + reg = read32((void *)gpio_address); reg |= GPIO_OUTPUT_ENABLE; write32((void *)(uintptr_t)gpio_num, reg); } diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index c5b7c8a..f5c84ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -29,103 +29,107 @@ #define GPIO_OUTPUT_ENABLE (1 << 23) /* GPIO_0 - GPIO_62 */ -#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500) -#define GPIO_0 (GPIO_BANK0_CONTROL + 0x00) -#define GPIO_1 (GPIO_BANK0_CONTROL + 0x04) -#define GPIO_2 (GPIO_BANK0_CONTROL + 0x08) -#define GPIO_3 (GPIO_BANK0_CONTROL + 0x0c) -#define GPIO_4 (GPIO_BANK0_CONTROL + 0x10) -#define GPIO_5 (GPIO_BANK0_CONTROL + 0x14) -#define GPIO_6 (GPIO_BANK0_CONTROL + 0x18) -#define GPIO_7 (GPIO_BANK0_CONTROL + 0x1c) -#define GPIO_8 (GPIO_BANK0_CONTROL + 0x20) -#define GPIO_9 (GPIO_BANK0_CONTROL + 0x24) -#define GPIO_10 (GPIO_BANK0_CONTROL + 0x28) -#define GPIO_11 (GPIO_BANK0_CONTROL + 0x2c) -#define GPIO_12 (GPIO_BANK0_CONTROL + 0x30) -#define GPIO_13 (GPIO_BANK0_CONTROL + 0x34) -#define GPIO_14 (GPIO_BANK0_CONTROL + 0x38) -#define GPIO_15 (GPIO_BANK0_CONTROL + 0x3c) -#define GPIO_16 (GPIO_BANK0_CONTROL + 0x40) -#define GPIO_17 (GPIO_BANK0_CONTROL + 0x44) -#define GPIO_18 (GPIO_BANK0_CONTROL + 0x48) -#define GPIO_19 (GPIO_BANK0_CONTROL + 0x4c) -#define GPIO_20 (GPIO_BANK0_CONTROL + 0x50) -#define GPIO_21 (GPIO_BANK0_CONTROL + 0x54) -#define GPIO_22 (GPIO_BANK0_CONTROL + 0x58) -#define GPIO_23 (GPIO_BANK0_CONTROL + 0x5c) -#define GPIO_24 (GPIO_BANK0_CONTROL + 0x60) -#define GPIO_25 (GPIO_BANK0_CONTROL + 0x64) -#define GPIO_26 (GPIO_BANK0_CONTROL + 0x68) -#define GPIO_39 (GPIO_BANK0_CONTROL + 0x9c) -#define GPIO_42 (GPIO_BANK0_CONTROL + 0xa8) +#define GPIO_BANK0_CONTROL(gpio) \ + (AMD_SB_ACPI_MMIO_ADDR + 0x1500 + (gpio * 4)) +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_39 39 +#define GPIO_42 42 /* GPIO_64 - GPIO_127 */ -#define GPIO_BANK1_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1600) -#define GPIO_64 (GPIO_BANK1_CONTROL + 0x00) -#define GPIO_65 (GPIO_BANK1_CONTROL + 0x04) -#define GPIO_66 (GPIO_BANK1_CONTROL + 0x08) -#define GPIO_67 (GPIO_BANK1_CONTROL + 0x0c) -#define GPIO_68 (GPIO_BANK1_CONTROL + 0x10) -#define GPIO_69 (GPIO_BANK1_CONTROL + 0x14) -#define GPIO_70 (GPIO_BANK1_CONTROL + 0x18) -#define GPIO_71 (GPIO_BANK1_CONTROL + 0x1c) -#define GPIO_72 (GPIO_BANK1_CONTROL + 0x20) -#define GPIO_74 (GPIO_BANK1_CONTROL + 0x28) -#define GPIO_75 (GPIO_BANK1_CONTROL + 0x2c) -#define GPIO_76 (GPIO_BANK1_CONTROL + 0x30) -#define GPIO_84 (GPIO_BANK1_CONTROL + 0x50) -#define GPIO_85 (GPIO_BANK1_CONTROL + 0x54) -#define GPIO_86 (GPIO_BANK1_CONTROL + 0x58) -#define GPIO_87 (GPIO_BANK1_CONTROL + 0x5c) -#define GPIO_88 (GPIO_BANK1_CONTROL + 0x60) -#define GPIO_89 (GPIO_BANK1_CONTROL + 0x64) -#define GPIO_90 (GPIO_BANK1_CONTROL + 0x68) -#define GPIO_91 (GPIO_BANK1_CONTROL + 0x6c) -#define GPIO_92 (GPIO_BANK1_CONTROL + 0x70) -#define GPIO_93 (GPIO_BANK1_CONTROL + 0x74) -#define GPIO_95 (GPIO_BANK1_CONTROL + 0x7c) -#define GPIO_96 (GPIO_BANK1_CONTROL + 0x80) -#define GPIO_97 (GPIO_BANK1_CONTROL + 0x84) -#define GPIO_98 (GPIO_BANK1_CONTROL + 0x88) -#define GPIO_99 (GPIO_BANK1_CONTROL + 0x8c) -#define GPIO_100 (GPIO_BANK1_CONTROL + 0x90) -#define GPIO_101 (GPIO_BANK1_CONTROL + 0x94) -#define GPIO_102 (GPIO_BANK1_CONTROL + 0x98) -#define GPIO_113 (GPIO_BANK1_CONTROL + 0xc4) -#define GPIO_114 (GPIO_BANK1_CONTROL + 0xc8) -#define GPIO_115 (GPIO_BANK1_CONTROL + 0xcc) -#define GPIO_116 (GPIO_BANK1_CONTROL + 0xd0) -#define GPIO_117 (GPIO_BANK1_CONTROL + 0xd4) -#define GPIO_118 (GPIO_BANK1_CONTROL + 0xd8) -#define GPIO_119 (GPIO_BANK1_CONTROL + 0xdc) -#define GPIO_120 (GPIO_BANK1_CONTROL + 0xe0) -#define GPIO_121 (GPIO_BANK1_CONTROL + 0xe4) -#define GPIO_122 (GPIO_BANK1_CONTROL + 0xe8) -#define GPIO_126 (GPIO_BANK1_CONTROL + 0xf8) +#define GPIO_BANK1_CONTROL(gpio) \ + (AMD_SB_ACPI_MMIO_ADDR + 0x1600 + ((gpio - 64) * 4)) +#define GPIO_64 64 +#define GPIO_65 65 +#define GPIO_66 66 +#define GPIO_67 67 +#define GPIO_68 68 +#define GPIO_69 69 +#define GPIO_70 70 +#define GPIO_71 71 +#define GPIO_72 72 +#define GPIO_74 74 +#define GPIO_75 75 +#define GPIO_76 76 +#define GPIO_84 84 +#define GPIO_85 85 +#define GPIO_86 86 +#define GPIO_87 87 +#define GPIO_88 88 +#define GPIO_89 89 +#define GPIO_90 90 +#define GPIO_91 91 +#define GPIO_92 92 +#define GPIO_93 93 +#define GPIO_95 95 +#define GPIO_96 96 +#define GPIO_97 97 +#define GPIO_98 98 +#define GPIO_99 99 +#define GPIO_100 100 +#define GPIO_101 101 +#define GPIO_102 102 +#define GPIO_113 113 +#define GPIO_114 114 +#define GPIO_115 115 +#define GPIO_116 116 +#define GPIO_117 117 +#define GPIO_118 118 +#define GPIO_119 119 +#define GPIO_120 120 +#define GPIO_121 121 +#define GPIO_122 122 +#define GPIO_126 126 /* GPIO_128 - GPIO_183 */ -#define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700) -#define GPIO_129 (GPIO_BANK2_CONTROL + 0x04) -#define GPIO_130 (GPIO_BANK2_CONTROL + 0x08) -#define GPIO_131 (GPIO_BANK2_CONTROL + 0x0c) -#define GPIO_132 (GPIO_BANK2_CONTROL + 0x10) -#define GPIO_133 (GPIO_BANK2_CONTROL + 0x14) -#define GPIO_134 (GPIO_BANK2_CONTROL + 0x18) -#define GPIO_135 (GPIO_BANK2_CONTROL + 0x1c) -#define GPIO_136 (GPIO_BANK2_CONTROL + 0x20) -#define GPIO_137 (GPIO_BANK2_CONTROL + 0x24) -#define GPIO_138 (GPIO_BANK2_CONTROL + 0x28) -#define GPIO_139 (GPIO_BANK2_CONTROL + 0x2c) -#define GPIO_140 (GPIO_BANK2_CONTROL + 0x30) -#define GPIO_141 (GPIO_BANK2_CONTROL + 0x34) -#define GPIO_142 (GPIO_BANK2_CONTROL + 0x38) -#define GPIO_143 (GPIO_BANK2_CONTROL + 0x3c) -#define GPIO_144 (GPIO_BANK2_CONTROL + 0x40) -#define GPIO_145 (GPIO_BANK2_CONTROL + 0x44) -#define GPIO_146 (GPIO_BANK2_CONTROL + 0x48) -#define GPIO_147 (GPIO_BANK2_CONTROL + 0x4c) -#define GPIO_148 (GPIO_BANK2_CONTROL + 0x50) +#define GPIO_BANK2_CONTROL(gpio) \ + (AMD_SB_ACPI_MMIO_ADDR + 0x1700 + ((gpio - 128) * 4)) +/* GPIO_128 Reserved */ +#define GPIO_129 129 +#define GPIO_130 130 +#define GPIO_131 131 +#define GPIO_132 132 +#define GPIO_133 133 +#define GPIO_134 134 +#define GPIO_135 135 +#define GPIO_136 136 +#define GPIO_137 137 +#define GPIO_138 138 +#define GPIO_139 139 +#define GPIO_140 140 +#define GPIO_141 141 +#define GPIO_142 142 +#define GPIO_143 143 +#define GPIO_144 144 +#define GPIO_145 145 +#define GPIO_146 146 +#define GPIO_147 147 +#define GPIO_148 148 typedef uint32_t gpio_t; -- To view, visit https://review.coreboot.org/21684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Gerrit-Change-Number: 21684 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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coreboot-gerrit September 2017