coreboot-gerrit July 2017

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Change in coreboot[master]: intel/cannonlake_rvp: Split RVP boards and SPD
by build bot (Jenkins) (Code Review) 08 Jul '17

08 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20503 ) Change subject: intel/cannonlake_rvp: Split RVP boards and SPD ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/56711/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/12271/ : SUCCESS -- To view, visit https://review.coreboot.org/20503 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Gerrit-Change-Number: 20503 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Jul 2017 01:44:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/cannonlake_rvp: Split RVP boards and SPD
by Lijian Zhao (Code Review) 08 Jul '17

08 Jul '17

Hello Andrey Petrov, Subrata Banik, John Zhao, Bora Guvendik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20503 to look at the new patch set (#2). Change subject: intel/cannonlake_rvp: Split RVP boards and SPD ...................................................................... intel/cannonlake_rvp: Split RVP boards and SPD Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/cannonlake_rvp/Kconfig.name M src/mainboard/intel/cannonlake_rvp/Makefile.inc M src/mainboard/intel/cannonlake_rvp/romstage.c A src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc A src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/spd.h A src/mainboard/intel/cannonlake_rvp/spd/spd_util.c A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 12 files changed, 339 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20503/2 -- To view, visit https://review.coreboot.org/20503 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Gerrit-Change-Number: 20503 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: intel/cannonlake_rvp: Split RVP boards and SPD
by build bot (Jenkins) (Code Review) 08 Jul '17

08 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20503 ) Change subject: intel/cannonlake_rvp: Split RVP boards and SPD ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/56710/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/12270/ : SUCCESS -- To view, visit https://review.coreboot.org/20503 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Gerrit-Change-Number: 20503 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Jul 2017 01:38:56 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: intel/cannonlake_rvp: Split RVP boards and SPD
by Lijian Zhao (Code Review) 08 Jul '17

08 Jul '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20503 Change subject: intel/cannonlake_rvp: Split RVP boards and SPD ...................................................................... intel/cannonlake_rvp: Split RVP boards and SPD Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/cannonlake_rvp/Kconfig.name M src/mainboard/intel/cannonlake_rvp/Makefile.inc M src/mainboard/intel/cannonlake_rvp/romstage.c A src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc A src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex A src/mainboard/intel/cannonlake_rvp/spd/spd.h A src/mainboard/intel/cannonlake_rvp/spd/spd_util.c A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 12 files changed, 339 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20503/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 54cd3f6..c59abcf 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -1,13 +1,19 @@ -if BOARD_INTEL_CANNONLAKE_RVP +if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_CANNONLAKE + select GENERIC_SPD_BIN config MAINBOARD_DIR string default "intel/cannonlake_rvp" + +config VARIANT_DIR + string + default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU + default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY config MAINBOARD_PART_NUMBER string @@ -16,6 +22,10 @@ config MAINBOARD_VENDOR string default "Intel" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config IFD_BIN_PATH string @@ -32,4 +42,8 @@ depends on HAVE_EC_BIN default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" +config DIMM_SPD_SIZE + int + default 512 + endif diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name index 4935603..1102e39 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig.name +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig.name @@ -1,2 +1,4 @@ -config BOARD_INTEL_CANNONLAKE_RVP - bool "Cannonlake DDR4 RVP" +config BOARD_INTEL_CANNONLAKE_RVPU + bool "Cannonlake U DDR4 RVP" +config BOARD_INTEL_CANNONLAKE_RVPY + bool "Cannonlake Y LPDDR4 RVP" diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index 75c34dd..dd8303f 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -1 +1,20 @@ -#Nothing here yet +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c index 1f58c2c..632bcb6 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage.c @@ -14,4 +14,48 @@ * GNU General Public License for more details. */ -//Nothing here yet, but file needed for build. +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = 0; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; /* DDR4 */ + spd_index = 1; + } + else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0; /* LPDDR4 */ + spd_index = 2; + } + + printk(BIOS_DEBUG,"SPD INDEX =0x%u\n",spd_index); + + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +} diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc new file mode 100644 index 0000000..656d5b9 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += samsung_ddr4_4GB # 1b001 Dual Channel 4GB +SPD_SOURCES += samsung_lpddr4_8GB # 2b001 Dual Channel 8GB +SPD_SOURCES += empty # 3b011 +SPD_SOURCES += empty # 4b100 +SPD_SOURCES += empty # 5b101 +SPD_SOURCES += empty # 6b110 +SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex new file mode 100644 index 0000000..d298629 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex @@ -0,0 +1,32 @@ +23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 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a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h new file mode 100644 index 0000000..f2b6f2a --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c new file mode 100644 index 0000000..ff6b09f --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdint.h> +#include <string.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map_u[2][12] = { + { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }; + + const u8 dq_map_y[2][12] = { + { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { + memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u)); + } + else { + memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y)); + } +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map_u[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + + const u8 dqs_map_y[2][8] = { + { 2, 0, 3, 1, 6, 5, 7, 4 }, + { 3, 1, 2, 0, 4, 5, 6, 7 } }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { + memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); + } + else { + memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + } +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 100, 100, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + + static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = { + 80, 40, 40, 40, 30 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { + memcpy(rcomp_strength_ptr, RcompTarget_U, sizeof(RcompTarget_U)); + } + else { + memcpy(rcomp_strength_ptr, RcompTarget_Y, sizeof(RcompTarget_Y)); + } +} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb new file mode 100644 index 0000000..c7001a4 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + end +end diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb new file mode 100644 index 0000000..c7001a4 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/20503 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Gerrit-Change-Number: 20503 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Initial board files
by build bot (Jenkins) (Code Review) 08 Jul '17

08 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20075 ) Change subject: mainboard/intel/cannonlake_rvp: Initial board files ...................................................................... Patch Set 9: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56709/ : UNSTABLE -- To view, visit https://review.coreboot.org/20075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Gerrit-Change-Number: 20075 Gerrit-PatchSet: 9 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Jul 2017 00:48:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Minimal changes to call FSPM
by build bot (Jenkins) (Code Review) 08 Jul '17

08 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20497 ) Change subject: soc/intel/cannonlake: Minimal changes to call FSPM ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56708/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12269/ : SUCCESS -- To view, visit https://review.coreboot.org/20497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Gerrit-Change-Number: 20497 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 09 Jul 2017 00:36:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Minimal changes to call FSPM
by Lijian Zhao (Code Review) 08 Jul '17

08 Jul '17

Hello Andrey Petrov, Subrata Banik, John Zhao, Bora Guvendik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20497 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Minimal changes to call FSPM ...................................................................... soc/intel/cannonlake: Minimal changes to call FSPM The following minimal changes will be needed to call into Fsp Memory Init 1.SA BARs need to be programmed. 2.Assume power state is S0. Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/include/soc/pm.h A src/soc/intel/cannonlake/include/soc/romstage.h A src/soc/intel/cannonlake/romstage/Makefile.inc A src/soc/intel/cannonlake/romstage/power_state.c A src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/romstage/systemagent.c 7 files changed, 192 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20497/2 -- To view, visit https://review.coreboot.org/20497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 Gerrit-Change-Number: 20497 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: samsung/lumpy: change HDA codec SSID to fix Windows
by build bot (Jenkins) (Code Review) 08 Jul '17

08 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20485 ) Change subject: samsung/lumpy: change HDA codec SSID to fix Windows ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56702/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12263/ : SUCCESS -- To view, visit https://review.coreboot.org/20485 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4195d00d6b18dcd0039747d9883cdf8e1a76f461 Gerrit-Change-Number: 20485 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Jul 2017 19:11:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/chell: remove non-existent touchscreen
by Martin Roth (Code Review) 08 Jul '17

08 Jul '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/20498 ) Change subject: google/chell: remove non-existent touchscreen ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20498 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I32619b7618bc0cdd99fa54fdda9bf2b5c1bb79a4 Gerrit-Change-Number: 20498 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 08 Jul 2017 19:04:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Makefile: update clean-utils & distclean-utils
by Martin Roth (Code Review) 08 Jul '17

08 Jul '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20494 ) Change subject: Makefile: update clean-utils & distclean-utils ...................................................................... Makefile: update clean-utils & distclean-utils Distclean-utils target was missing a backslash at the end to continue on the next line. Change-Id: I2bddff342f9c0fcb27e9b40ac94377c60ba5b7fe Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/20494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Makefile b/Makefile index 87576c8..31fb3ad 100644 --- a/Makefile +++ b/Makefile @@ -417,10 +417,12 @@ rm -f tags clean-utils: - $(foreach tool, $(TOOLLIST), $(MAKE) -C util/$(tool) clean MFLAGS= MAKEFLAGS= ;) + $(foreach tool, $(TOOLLIST), \ + $(MAKE) -C util/$(tool) clean MFLAGS= MAKEFLAGS= ;) distclean-utils: - $(foreach tool, $(TOOLLIST), $(MAKE) -C util/$(tool) distclean MFLAGS= MAKEFLAGS= ; + $(foreach tool, $(TOOLLIST), \ + $(MAKE) -C util/$(tool) distclean MFLAGS= MAKEFLAGS= ; \ rm -f /util/$(tool)/junit.xml;) distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils -- To view, visit https://review.coreboot.org/20494 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2bddff342f9c0fcb27e9b40ac94377c60ba5b7fe Gerrit-Change-Number: 20494 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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