coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: util/crossgcc: Fix building gcc 6.3.0 with clang
by build bot (Jenkins) (Code Review) 26 Jun '17

26 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20366 ) Change subject: util/crossgcc: Fix building gcc 6.3.0 with clang ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56191/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11793/ : SUCCESS https://qa.coreboot.org/job/coreboot-toolchain/314/ : SUCCESS -- To view, visit https://review.coreboot.org/20366 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1930bb01dd62bd6abf0688b118236db2a9299e40 Gerrit-Change-Number: 20366 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Jun 2017 06:37:30 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Use word access for power state ...
by build bot (Jenkins) (Code Review) 26 Jun '17

26 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20364 ) Change subject: soc/intel/skylake: storage: Use word access for power state registers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56192/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11794/ : SUCCESS -- To view, visit https://review.coreboot.org/20364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Gerrit-Change-Number: 20364 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Jun 2017 06:06:48 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Use word access for power state ...
by Duncan Laurie (Code Review) 26 Jun '17

26 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20364 to look at the new patch set (#2). Change subject: soc/intel/skylake: storage: Use word access for power state registers ...................................................................... soc/intel/skylake: storage: Use word access for power state registers In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/acpi/scs.asl 1 file changed, 17 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20364/2 -- To view, visit https://review.coreboot.org/20364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Gerrit-Change-Number: 20364 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: util/crossgcc: Fix building gcc 6.3.0 with clang
by Patrick Georgi (Code Review) 26 Jun '17

26 Jun '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/20366 Change subject: util/crossgcc: Fix building gcc 6.3.0 with clang ...................................................................... util/crossgcc: Fix building gcc 6.3.0 with clang It assumes that __builtin_longjmp takes a void **, which is decidedly distinctive from void *. Change-Id: I1930bb01dd62bd6abf0688b118236db2a9299e40 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- A util/crossgcc/patches/gcc-6.3.0_ada-raise.patch 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/20366/1 diff --git a/util/crossgcc/patches/gcc-6.3.0_ada-raise.patch b/util/crossgcc/patches/gcc-6.3.0_ada-raise.patch new file mode 100644 index 0000000..a081957 --- /dev/null +++ b/util/crossgcc/patches/gcc-6.3.0_ada-raise.patch @@ -0,0 +1,11 @@ +--- gcc-6.3.0/gcc/ada/raise.c.orig 2017-06-24 07:06:41.524685169 +0200 ++++ gcc-6.3.0/gcc/ada/raise.c 2017-06-24 07:07:12.945162120 +0200 +@@ -55,7 +55,7 @@ + void + _gnat_builtin_longjmp (void *ptr, int flag ATTRIBUTE_UNUSED) + { +- __builtin_longjmp (ptr, 1); ++ __builtin_longjmp ((void **)ptr, 1); + } + #endif + -- To view, visit https://review.coreboot.org/20366 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1930bb01dd62bd6abf0688b118236db2a9299e40 Gerrit-Change-Number: 20366 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: crossgcc: Fix building with clang++ in the presence of gcc
by Patrick Georgi (Code Review) 26 Jun '17

26 Jun '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/20365 Change subject: crossgcc: Fix building with clang++ in the presence of gcc ...................................................................... crossgcc: Fix building with clang++ in the presence of gcc Some environments (<grumble>cros_sdk</grumble>) provide gcc as $CC and clang++ as $CXX. The latter needs the higher bracket-depth while the former has no idea what it means, so tell CC and CXX individually. Change-Id: I72b75fb9bb5df3a9b1561ee8821ec43ada29b24f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- M util/crossgcc/buildgcc 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/20365/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 4d1f25a..01da659 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -621,7 +621,9 @@ build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ - HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" + CLANGFLAGS="-fbracket-depth=1024" + $CXX --version | grep clang >/dev/null 2>&1 && \ + CLANGCXXFLAGS="-fbracket-depth=1024" # GCC does not honor HOSTCFLAGS at all. CFLAGS are used for # both target and host object files. @@ -630,9 +632,12 @@ # libiberty is not compiled with CFLAGS_FOR_BUILD. # Also set the CXX version of the flags because GCC is now compiled # using C++. - CC="$CC" CFLAGS_FOR_TARGET="-O2 -Dinhibit_libc" CFLAGS="$HOSTCFLAGS" \ - CFLAGS_FOR_BUILD="$HOSTCFLAGS" CXXFLAGS="$HOSTCFLAGS" \ - CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" ../gcc-${GCC_VERSION}/configure \ + CC="$CC" CFLAGS_FOR_TARGET="-O2 -Dinhibit_libc" + CFLAGS="$HOSTCFLAGS $CLANGFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS $CLANGFLAGS" \ + CXXFLAGS="$HOSTCFLAGS $CLANGCXXFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS $CLANGCXXFLAGS" \ + ../gcc-${GCC_VERSION}/configure \ --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ --target=${TARGETARCH} --disable-werror --disable-shared \ --enable-lto --enable-plugins --enable-gold --enable-ld=default \ -- To view, visit https://review.coreboot.org/20365 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I72b75fb9bb5df3a9b1561ee8821ec43ada29b24f Gerrit-Change-Number: 20365 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Use word access for power state ...
by build bot (Jenkins) (Code Review) 26 Jun '17

26 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20364 ) Change subject: soc/intel/skylake: storage: Use word access for power state registers ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56189/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/11791/ : SUCCESS -- To view, visit https://review.coreboot.org/20364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Gerrit-Change-Number: 20364 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Jun 2017 04:18:58 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Add 2ms delay before exiting D3
by build bot (Jenkins) (Code Review) 26 Jun '17

26 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20363 ) Change subject: soc/intel/skylake: storage: Add 2ms delay before exiting D3 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56188/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11790/ : SUCCESS -- To view, visit https://review.coreboot.org/20363 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Gerrit-Change-Number: 20363 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Jun 2017 04:17:48 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Use word access for power state ...
by Duncan Laurie (Code Review) 26 Jun '17

26 Jun '17

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20364 Change subject: soc/intel/skylake: storage: Use word access for power state registers ...................................................................... soc/intel/skylake: storage: Use word access for power state registers In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/acpi/scs.asl 1 file changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20364/1 diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index c2f50cc..240d2b8 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -21,12 +21,13 @@ Name (_ADR, 0x001E0004) Name (_DDN, "eMMC Controller") Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + Name (TEMP, 0) OperationRegion (EMCR, PCI_Config, 0x00, 0x100) - Field (EMCR, DWordAcc, NoLock, Preserve) + Field (EMCR, WordAcc, NoLock, Preserve) { Offset (0x84), /* PMECTRLSTATUS */ - D0D3, 2, /* POWERSTATE */ + PMCR, 16, Offset (0xa2), /* PG_CONFIG */ , 2, PGEN, 1, /* PG_ENABLE */ @@ -98,10 +99,9 @@ /* Enable Power Gate */ Store (1, ^PGEN) - /* Set Power State to D0 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, ^TEMP) } } @@ -110,12 +110,13 @@ { Name (_ADR, 0x001E0006) Name (_DDN, "SD Controller") + Name (TEMP, 0) OperationRegion (SDCR, PCI_Config, 0x00, 0x100) - Field (SDCR, DWordAcc, NoLock, Preserve) + Field (SDCR, WordAcc, NoLock, Preserve) { Offset (0x84), /* PMECTRLSTATUS */ - D0D3, 2, /* POWERSTATE */ + PMCR, 16, Offset (0xa2), /* PG_CONFIG */ , 2, PGEN, 1, /* PG_ENABLE */ @@ -138,14 +139,13 @@ ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) Sleep (2) - /* Set bits 31, 6, 2, 0 */ + /* Set bits 8, 7, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x00000185) Sleep (2) /* Set Power State to D0 */ - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, ^TEMP) } Method (_PS3, 0, Serialized) @@ -153,10 +153,9 @@ /* Enable Power Gate */ Store (1, ^PGEN) - /* Set Power State to D0 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, ^TEMP) /* Enable 20K pull-down on CLK, CMD and DAT lines */ ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) -- To view, visit https://review.coreboot.org/20364 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Gerrit-Change-Number: 20364 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

1 0

Change in coreboot[master]: soc/intel/skylake: storage: Add 2ms delay before exiting D3
by Duncan Laurie (Code Review) 26 Jun '17

26 Jun '17

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/20363 Change subject: soc/intel/skylake: storage: Add 2ms delay before exiting D3 ...................................................................... soc/intel/skylake: storage: Add 2ms delay before exiting D3 For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/soc/intel/skylake/acpi/scs.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/20363/1 diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 1f89689..c2f50cc 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -85,6 +85,7 @@ /* Set bits 31, 6, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x80000045) + Sleep (2) /* Set Power State to D0 */ Store (Zero, Local0) @@ -139,6 +140,7 @@ /* Set bits 31, 6, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x00000185) + Sleep (2) /* Set Power State to D0 */ Store (Zero, Local0) -- To view, visit https://review.coreboot.org/20363 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Gerrit-Change-Number: 20363 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

1 0

Change in coreboot[master]: 3rdparty/chromeec: Update submodule to upstream master
by build bot (Jenkins) (Code Review) 26 Jun '17

26 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20362 ) Change subject: 3rdparty/chromeec: Update submodule to upstream master ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56187/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11788/ : SUCCESS -- To view, visit https://review.coreboot.org/20362 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I864679360bd3b211b6883a662e20812b49aefbba Gerrit-Change-Number: 20362 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Jun 2017 03:48:55 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017