coreboot-gerrit June 2017

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Change in coreboot[master]: src/include/device: Add System Agent (SA) device ids
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Hello Aaron Durbin, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19794 to look at the new patch set (#4). Change subject: src/include/device: Add System Agent (SA) device ids ...................................................................... src/include/device: Add System Agent (SA) device ids Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19794/4 -- To view, visit https://review.coreboot.org/19794 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Remove unused PCI ID from SOC header
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19927 ) Change subject: soc/intel/apollolake: Remove unused PCI ID from SOC header ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54684/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10389/ : SUCCESS -- To view, visit https://review.coreboot.org/19927 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3a86256641f4b877de32ca81dfdaef4e9d49334a Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19793 ) Change subject: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54685/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10390/ : SUCCESS -- To view, visit https://review.coreboot.org/19793 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iace1cf786b08221c3955101186509ac5161c3841 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19668 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 5: (24 comments) https://review.coreboot.org/#/c/19668/5/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/systemagent.h: Line 62: size_t count); > Comment your exposed functions. Really his entire file needs better comment Done Line 67: #if ENV_RAMSTAGE > I really hate guarding things like this, and I've yet to see a good reason Done Line 70: int soc_add_fixed_mmio_resources(device_t dev); > Don't use device_t here. use struct device *. Done Line 76: size_t size; > What's the significance of this filed? Like functions, these exposed struct Done PS5, Line 85: int > bool? Done PS5, Line 94: BAR > at REG in pci space? Otherwise it's purely a value found at reg? Done https://review.coreboot.org/#/c/19668/5/src/soc/intel/common/block/systemag… File src/soc/intel/common/block/systemagent/systemagent.c: Line 43: return 0; > we should use index as return Done Line 46: __attribute__((weak)) void soc_add_imr_resources(device_t dev, int index) > got it, you want to unify behavior, i had focused on function caling order. Done Line 55: #define DPR_SIZE_MASK 0xff0 > Yes, I know. It was more about how this doesn't apply to all chipsets. A co Done Line 57: int sa_get_pcie_base_addr(device_t dev, unsigned int index, uintptr_t *base, > But you don't have to. Done PS5, Line 84: if( > space between if and ( Done PS5, Line 93: len > i guess this is a miss, we don't need to get the len, purpose for this API Done PS5, Line 115: *len) > But we know base and length for nearly all the entries in such a table. We Done Line 156: IORESOURCE_ASSIGNED; > mmio_resource() Done Line 166: static void read_map_entry(device_t dev, const struct sa_map_entry *entry, > But why complicate this further? Why not provide an array of Done Line 306: IORESOURCE_ASSIGNED; > Why isn't reserved_ram_resource() and ram_resource() being used? Done PS5, Line 310: SA_TSEG_REG > That would be helpful documentation in the header file about the surface ar Done PS5, Line 337: (0xa0000 / KiB) > parens not needed Done Line 338: (0xc0000 - 0xa0000) / KiB); > same line Done PS5, Line 339: (0xc0000 / KiB), > parens not needed Done PS5, Line 365: const struct sa_mmio_descriptor *sa_imr_resources > All that was used out of this structure is a index and an optional descript Done Line 384: resource->base = (base & 0x0fffffff) * KiB; > Why isn't reserved_ram_resource being used here? Is this so one can spew ou Done Line 422: int index = 0; > No reason to set this to 0. It's assigned below. Done https://review.coreboot.org/#/c/19668/5/src/soc/intel/common/block/systemag… File src/soc/intel/common/block/systemagent/systemagent_early.c: Line 111: (unsigned long)base); > So we're going to see that these messages spewed out on every boot? What is i have now guarded against SA_DEBUG, to avoid every boot more debug log. now its more over user debug interest. -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Hello V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19668 to look at the new patch set (#6). Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... soc/intel/common/block: Add Intel common systemagent support Add Intel common systemagent support for romstage and ramstage. Include soc specific macros need to compile systemagent common code. Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c A src/soc/intel/common/block/systemagent/systemagent_def.h A src/soc/intel/common/block/systemagent/systemagent_early.c 6 files changed, 612 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19668/6 -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Use common systemagent code
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19796 to look at the new patch set (#4). Change subject: soc/intel/skylake: Use common systemagent code ...................................................................... soc/intel/skylake: Use common systemagent code This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 34 insertions(+), 441 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19796/4 -- To view, visit https://review.coreboot.org/19796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Use common systemagent code
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19795 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Use common systemagent code ...................................................................... soc/intel/apollolake: Use common systemagent code This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c A src/soc/intel/apollolake/include/soc/pci_ids.h M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/apollolake/northbridge.c M src/soc/intel/apollolake/romstage.c 6 files changed, 71 insertions(+), 170 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19795/4 -- To view, visit https://review.coreboot.org/19795 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Remove unused PCI ID from SOC header
by Subrata Banik (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19927 to look at the new patch set (#2). Change subject: soc/intel/apollolake: Remove unused PCI ID from SOC header ...................................................................... soc/intel/apollolake: Remove unused PCI ID from SOC header SoC defined PCI IDs are not getting used after migrated to common pci_ids.h header for PCI related IDs. Change-Id: I3a86256641f4b877de32ca81dfdaef4e9d49334a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/dsp.c M src/soc/intel/apollolake/graphics.c D src/soc/intel/apollolake/include/soc/pci_ids.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/apollolake/northbridge.c M src/soc/intel/apollolake/p2sb.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/sram.c M src/soc/intel/common/block/cse/cse.c 9 files changed, 8 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19927/2 -- To view, visit https://review.coreboot.org/19927 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3a86256641f4b877de32ca81dfdaef4e9d49334a Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 for GLK
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19746 ) Change subject: soc/intel/apollolake: configure RAPL PL1 for GLK ...................................................................... Patch Set 5: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54683/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10388/ : SUCCESS -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GL...
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19739 ) Change subject: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. ...................................................................... Patch Set 8: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54682/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10387/ : SUCCESS -- To view, visit https://review.coreboot.org/19739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit June 2017