coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: soc/intel/apollolake: Use Intel timer common code
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19913 ) Change subject: soc/intel/apollolake: Use Intel timer common code ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10504/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54802/ : SUCCESS -- To view, visit https://review.coreboot.org/19913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Gerrit-Change-Number: 19913 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:55:54 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Use Intel timer common code
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19913 ) Change subject: soc/intel/apollolake: Use Intel timer common code ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54800/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10502/ : SUCCESS -- To view, visit https://review.coreboot.org/19913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Gerrit-Change-Number: 19913 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:32:43 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common: Add common Intel timer code
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19911 ) Change subject: soc/intel/common: Add common Intel timer code ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10499/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54798/ : SUCCESS -- To view, visit https://review.coreboot.org/19911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Gerrit-Change-Number: 19911 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:27:46 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Add config for cpu base clock frequency
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20017 ) Change subject: soc/intel/apollolake: Add config for cpu base clock frequency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10503/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54801/ : SUCCESS -- To view, visit https://review.coreboot.org/20017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1 Gerrit-Change-Number: 20017 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:27:32 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Use Intel timer common code
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19912 ) Change subject: soc/intel/skylake: Use Intel timer common code ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10500/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54797/ : SUCCESS -- To view, visit https://review.coreboot.org/19912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Gerrit-Change-Number: 19912 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:25:47 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Add config for cpu base clock frequency
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20016 ) Change subject: soc/intel/skylake: Add config for cpu base clock frequency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10501/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54799/ : SUCCESS -- To view, visit https://review.coreboot.org/20016 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Gerrit-Change-Number: 20016 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:23:50 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20002 ) Change subject: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10498/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54796/ : SUCCESS -- To view, visit https://review.coreboot.org/20002 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Gerrit-Change-Number: 20002 Gerrit-PatchSet: 3 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:19:47 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Add config for cpu base clock frequency
by Aamir Bohra (Code Review) 02 Jun '17

02 Jun '17

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/20017 Change subject: soc/intel/apollolake: Add config for cpu base clock frequency ...................................................................... soc/intel/apollolake: Add config for cpu base clock frequency Add config for cpu base clock frequency(Mhz), use and clean up code. Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/tsc_freq.c 3 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/20017/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 56f0d20..fe72c07 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -322,4 +322,8 @@ string default "aplk" +config CPU_BCLK_MHZ + int + default 100 + endif diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 3391597..0900eef 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -32,8 +32,6 @@ #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 -#define BASE_CLOCK_MHZ 100 - /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index f91a047..885311c 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -26,7 +26,7 @@ unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); + return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff)); } void set_max_freq(void) -- To view, visit https://review.coreboot.org/20017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I724c48c11796aa942295d4f19cc629d4c13647e1 Gerrit-Change-Number: 20017 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Add config for cpu base clock frequency
by Aamir Bohra (Code Review) 02 Jun '17

02 Jun '17

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/20016 Change subject: soc/intel/skylake: Add config for cpu base clock frequency ...................................................................... soc/intel/skylake: Add config for cpu base clock frequency Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/tsc_freq.c 6 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/20016/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 80cdde6..067e833 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -323,4 +323,8 @@ int default 2 +config CPU_BCLK_MHZ + int + default 100 + endif diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 77fbb48..f9b39f2 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -410,7 +410,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * CPU_BCLK; + clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; /* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -474,7 +474,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; + clock = ratio * CONFIG_CPU_BCLK_MHZ; acpigen_write_PSS_package( clock, /* MHz */ diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 040e847..23b4b18 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -138,5 +138,5 @@ wrmsr(MSR_IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0572413..95d9ad9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -320,7 +320,7 @@ wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } static void set_energy_perf_bias(u8 policy) diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 9171172..f6803c9 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -34,9 +34,6 @@ #define CPUID_KABYLAKE_HA0 0x506e8 #define CPUID_KABYLAKE_HB0 0x906e9 -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - /* Latency times in units of 1024ns. */ #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 diff --git a/src/soc/intel/skylake/tsc_freq.c b/src/soc/intel/skylake/tsc_freq.c index 9ebe3cb..8a4ff46 100644 --- a/src/soc/intel/skylake/tsc_freq.c +++ b/src/soc/intel/skylake/tsc_freq.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <soc/cpu.h> #include <soc/msr.h> unsigned long tsc_freq_mhz(void) @@ -25,5 +24,5 @@ msr_t platform_info; platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); + return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff); } -- To view, visit https://review.coreboot.org/20016 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Gerrit-Change-Number: 20016 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19668 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10495/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54793/ : SUCCESS -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-Change-Number: 19668 Gerrit-PatchSet: 10 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jun 2017 14:10:21 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017