coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/broadwell: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 02 Jun '17

02 Jun '17

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19969 to look at the new patch set (#2). Change subject: soc/broadwell: add ACPI method to generate USB port info ...................................................................... soc/broadwell: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/acpi/xhci.asl 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19969/2 -- To view, visit https://review.coreboot.org/19969 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Gerrit-Change-Number: 19969 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 for GLK
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19746 ) Change subject: soc/intel/apollolake: configure RAPL PL1 for GLK ...................................................................... Patch Set 6: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54815/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10516/ : SUCCESS -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-Change-Number: 19746 Gerrit-PatchSet: 6 Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:50:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: configure p-unit registers for GLK
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19742 ) Change subject: soc/intel/apollolake: configure p-unit registers for GLK ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54814/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10515/ : SUCCESS -- To view, visit https://review.coreboot.org/19742 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02bad173c5c3c16d00ffe58ce73084e5c0c002fe Gerrit-Change-Number: 19742 Gerrit-PatchSet: 2 Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:43:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/glkrvp: Add support for GLKRVP
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19604 ) Change subject: mainboard/intel/glkrvp: Add support for GLKRVP ...................................................................... Patch Set 45: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54812/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10513/ : SUCCESS -- To view, visit https://review.coreboot.org/19604 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Gerrit-Change-Number: 19604 Gerrit-PatchSet: 45 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:34:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/cmos: Remove unused option and checksum fix
by Philipp Deppenwiese (Code Review) 02 Jun '17

02 Jun '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19955 ) Change subject: mb/lenovo/*/cmos: Remove unused option and checksum fix ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19955 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55 Gerrit-Change-Number: 19955 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:31:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Bring in delta for GLK SOC
by build bot (Jenkins) (Code Review) 02 Jun '17

02 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19603 ) Change subject: soc/intel/apollolake: Bring in delta for GLK SOC ...................................................................... Patch Set 65: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54811/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10512/ : SUCCESS -- To view, visit https://review.coreboot.org/19603 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Gerrit-Change-Number: 19603 Gerrit-PatchSet: 65 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:31:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/rambi: disable PCI device for unused i2c buses
by Martin Roth (Code Review) 02 Jun '17

02 Jun '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19956 ) Change subject: google/rambi: disable PCI device for unused i2c buses ...................................................................... google/rambi: disable PCI device for unused i2c buses Light sensor isn't used and ACPI already removed, so disable I2C5 bus interface as well. Disable I2C6 for devices without a touchscreen Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19956 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/rambi/variants/clapper/devicetree.cb M src/mainboard/google/rambi/variants/enguarde/devicetree.cb M src/mainboard/google/rambi/variants/glimmer/devicetree.cb M src/mainboard/google/rambi/variants/gnawty/devicetree.cb M src/mainboard/google/rambi/variants/heli/devicetree.cb M src/mainboard/google/rambi/variants/kip/devicetree.cb M src/mainboard/google/rambi/variants/ninja/devicetree.cb M src/mainboard/google/rambi/variants/quawks/devicetree.cb M src/mainboard/google/rambi/variants/rambi/devicetree.cb M src/mainboard/google/rambi/variants/squawks/devicetree.cb M src/mainboard/google/rambi/variants/swanky/devicetree.cb 11 files changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/rambi/variants/clapper/devicetree.cb b/src/mainboard/google/rambi/variants/clapper/devicetree.cb index a95ddd1..13902b0 100644 --- a/src/mainboard/google/rambi/variants/clapper/devicetree.cb +++ b/src/mainboard/google/rambi/variants/clapper/devicetree.cb @@ -59,7 +59,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb index f3792fe..89929b0 100644 --- a/src/mainboard/google/rambi/variants/enguarde/devicetree.cb +++ b/src/mainboard/google/rambi/variants/enguarde/devicetree.cb @@ -71,8 +71,8 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 off end # I2C6 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE device pci 1b.0 on end # HDA diff --git a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb index bf01cd9..5148225 100644 --- a/src/mainboard/google/rambi/variants/glimmer/devicetree.cb +++ b/src/mainboard/google/rambi/variants/glimmer/devicetree.cb @@ -68,7 +68,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb index bb6fcad..0024679 100644 --- a/src/mainboard/google/rambi/variants/gnawty/devicetree.cb +++ b/src/mainboard/google/rambi/variants/gnawty/devicetree.cb @@ -71,8 +71,8 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 on end # I2C6 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE device pci 1b.0 on end # HDA diff --git a/src/mainboard/google/rambi/variants/heli/devicetree.cb b/src/mainboard/google/rambi/variants/heli/devicetree.cb index d9b27e6..8b3c83f 100644 --- a/src/mainboard/google/rambi/variants/heli/devicetree.cb +++ b/src/mainboard/google/rambi/variants/heli/devicetree.cb @@ -72,8 +72,8 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE device pci 1b.0 on end # HDA diff --git a/src/mainboard/google/rambi/variants/kip/devicetree.cb b/src/mainboard/google/rambi/variants/kip/devicetree.cb index f4e0a91..d1d6beb 100644 --- a/src/mainboard/google/rambi/variants/kip/devicetree.cb +++ b/src/mainboard/google/rambi/variants/kip/devicetree.cb @@ -71,7 +71,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/ninja/devicetree.cb b/src/mainboard/google/rambi/variants/ninja/devicetree.cb index 6d56130..5c9595c 100644 --- a/src/mainboard/google/rambi/variants/ninja/devicetree.cb +++ b/src/mainboard/google/rambi/variants/ninja/devicetree.cb @@ -73,7 +73,7 @@ device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 device pci 18.5 off end # I2C5 - device pci 18.6 off end # I2C6 + device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE device pci 1b.0 on end # HDA diff --git a/src/mainboard/google/rambi/variants/quawks/devicetree.cb b/src/mainboard/google/rambi/variants/quawks/devicetree.cb index cc5146d..320b59b 100644 --- a/src/mainboard/google/rambi/variants/quawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/quawks/devicetree.cb @@ -68,7 +68,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/rambi/devicetree.cb b/src/mainboard/google/rambi/variants/rambi/devicetree.cb index 5914a62..ddd1914 100644 --- a/src/mainboard/google/rambi/variants/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/variants/rambi/devicetree.cb @@ -72,7 +72,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/squawks/devicetree.cb b/src/mainboard/google/rambi/variants/squawks/devicetree.cb index 400a551..26a915d 100644 --- a/src/mainboard/google/rambi/variants/squawks/devicetree.cb +++ b/src/mainboard/google/rambi/variants/squawks/devicetree.cb @@ -68,7 +68,7 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 + device pci 18.5 off end # I2C5 device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE diff --git a/src/mainboard/google/rambi/variants/swanky/devicetree.cb b/src/mainboard/google/rambi/variants/swanky/devicetree.cb index 5e78a10..db21bd6 100644 --- a/src/mainboard/google/rambi/variants/swanky/devicetree.cb +++ b/src/mainboard/google/rambi/variants/swanky/devicetree.cb @@ -71,8 +71,8 @@ device pci 18.2 on end # I2C2 device pci 18.3 off end # I2C3 device pci 18.4 off end # I2C4 - device pci 18.5 on end # I2C5 - device pci 18.6 on end # I2C6 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE device pci 1b.0 on end # HDA -- To view, visit https://review.coreboot.org/19956 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4 Gerrit-Change-Number: 19956 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/baytrail: add ACPI method to generate USB port info
by Martin Roth (Code Review) 02 Jun '17

02 Jun '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19973 ) Change subject: soc/baytrail: add ACPI method to generate USB port info ...................................................................... soc/baytrail: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19973 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/baytrail/acpi/xhci.asl 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: Martin Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index bef0b9f..d3c0083 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -23,6 +23,23 @@ Device (RHUB) { Name (_ADR, 0x00000000) + + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + Device (PRT1) { Name (_ADR, 1) } Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } -- To view, visit https://review.coreboot.org/19973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Gerrit-Change-Number: 19973 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/baytrail: add missing USB port defs
by Martin Roth (Code Review) 02 Jun '17

02 Jun '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19972 ) Change subject: soc/baytrail: add missing USB port defs ...................................................................... soc/baytrail: add missing USB port defs Add device/address stub for XHCI USB port 7. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19972 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/intel/baytrail/acpi/xhci.asl 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index dbd3447..bef0b9f 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -27,5 +27,6 @@ Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } Device (PRT4) { Name (_ADR, 4) } + Device (SSP1) { Name (_ADR, 7) } } } -- To view, visit https://review.coreboot.org/19972 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9 Gerrit-Change-Number: 19972 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/broadwell: add ACPI method to generate USB port info
by Martin Roth (Code Review) 02 Jun '17

02 Jun '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19969 ) Change subject: soc/broadwell: add ACPI method to generate USB port info ...................................................................... Patch Set 1: -Code-Review Needs to be rebased manually. -- To view, visit https://review.coreboot.org/19969 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Gerrit-Change-Number: 19969 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Jun 2017 16:29:16 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017