coreboot-gerrit June 2017

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Change in coreboot[master]: mainboard/google/poppy: Add support for ELAN device
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20040 ) Change subject: mainboard/google/poppy: Add support for ELAN device ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10575/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/54875/ : ABORTED -- To view, visit https://review.coreboot.org/20040 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Gerrit-Change-Number: 20040 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Jun 2017 16:20:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: spi: Remove unused/unnecessary spi_init function definitions
by Furquan Shaikh (Code Review) 05 Jun '17

05 Jun '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20039 Change subject: spi: Remove unused/unnecessary spi_init function definitions ...................................................................... spi: Remove unused/unnecessary spi_init function definitions Remove spi_init definitions which: 1. Do nothing 2. Set static global variables to 0 Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/imgtec/pistachio/spi.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/samsung/exynos5420/spi.c M src/southbridge/amd/sb700/spi.c 5 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20039/1 diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index bfd982c..7e1a7a6 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -410,13 +410,6 @@ return SPIM_OK; } -/* Initialization, must be called once on start up */ -void spi_init(void) -{ - /* Clear everything just in case */ - memset(img_spi_slaves, 0, sizeof(img_spi_slaves)); -} - /* Claim the bus and prepare it for communication */ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 157903c..3dc6022 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -201,12 +201,6 @@ static struct ipq_spi_slave spi_slave_pool[2]; -void spi_init(void) -{ - /* just in case */ - memset(spi_slave_pool, 0, sizeof(spi_slave_pool)); -} - static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) { struct ipq_spi_slave *ds; diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index c20ad9a..f9a89fc 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -493,12 +493,6 @@ }; static struct ipq_spi_slave spi_slave_pool[2]; -void spi_init() -{ - /* just in case */ - memset(spi_slave_pool, 0, sizeof(spi_slave_pool)); -} - static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) { struct ipq_spi_slave *ds; diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index fa53c0f..2023b10 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -95,10 +95,6 @@ setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); } -void spi_init(void) -{ -} - static void exynos_spi_init(struct exynos_spi *regs) { // Set FB_CLK_SEL. diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index df44c04..caddfc8 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -35,11 +35,6 @@ return pci_read_config32(dev, 0xa0) & ~0x1f; } -void spi_init(void) -{ - /* Not needed */ -} - static void reset_internal_fifo_pointer(void) { uint32_t spibar = get_spi_bar(); -- To view, visit https://review.coreboot.org/20039 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If4c0cdbe2271fc7561becd87ad3b96bd45e77430 Gerrit-Change-Number: 20039 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/poppy: Add support for ELAN device
by Furquan Shaikh (Code Review) 05 Jun '17

05 Jun '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20040 Change subject: mainboard/google/poppy: Add support for ELAN device ...................................................................... mainboard/google/poppy: Add support for ELAN device BUG=b:62331218 Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/20040/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index c38bf93..f070363 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -206,6 +206,16 @@ device pci 14.2 on end # Thermal Subsystem device pci 15.0 on chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic register "hid" = ""ATML0001"" register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" -- To view, visit https://review.coreboot.org/20040 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id91a41743330c9e356293cfda7b2e3743dcd480c Gerrit-Change-Number: 20040 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake: [WIP] Use CPU common library code
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: [WIP] Use CPU common library code ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10572/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54872/ : SUCCESS -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-Change-Number: 19827 Gerrit-PatchSet: 7 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2017 15:32:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: [WIP] Use CPU common library code
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: [WIP] Use CPU common library code ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10570/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54870/ : SUCCESS -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-Change-Number: 19566 Gerrit-PatchSet: 11 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2017 15:27:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Rename ACPI Base Address and Size Macro
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20038 ) Change subject: soc/intel/apollolake: Rename ACPI Base Address and Size Macro ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10573/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54873/ : SUCCESS -- To view, visit https://review.coreboot.org/20038 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Gerrit-Change-Number: 20038 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2017 15:25:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP] Add Intel common CPU library code
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: [WIP] Add Intel common CPU library code ...................................................................... Patch Set 13: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10569/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54869/ : SUCCESS -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-Change-Number: 19540 Gerrit-PatchSet: 13 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2017 15:23:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init
by build bot (Jenkins) (Code Review) 05 Jun '17

05 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20037 ) Change subject: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10571/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54871/ : SUCCESS -- To view, visit https://review.coreboot.org/20037 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Gerrit-Change-Number: 20037 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 05 Jun 2017 15:22:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Rename ACPI Base Address and Size Macro
by Barnali Sarkar (Code Review) 05 Jun '17

05 Jun '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20038 Change subject: soc/intel/apollolake: Rename ACPI Base Address and Size Macro ...................................................................... soc/intel/apollolake: Rename ACPI Base Address and Size Macro Renaming these two Macros to help use Common Code - ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS ACPI_PMIO_SIZE --> ACPI_BASE_SIZE Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/common/smihandler.c 9 files changed, 58 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20038/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 6588488..1826b48 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -85,7 +85,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_PMIO_BASE; + const uint16_t pmbase = ACPI_BASE_ADDRESS; /* Use ACPI 3.0 revision. */ fadt->header.revision = ACPI_FADT_REV_ACPI_3_0; @@ -275,7 +275,7 @@ uint16_t soc_get_acpi_base_address(void) { - return ACPI_PMIO_BASE; + return ACPI_BASE_ADDRESS; } static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index cb151bd..8aeaef6 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -32,7 +32,7 @@ Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) - IO (Decode16, ACPI_PMIO_BASE, PMIO_LIMIT, + IO (Decode16, ACPI_BASE_ADDRESS, PMIO_LIMIT, 0x04, PMIO_LENGTH) Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 5c059d9..705567a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -56,7 +56,7 @@ /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PCH_DEV_PMC; - pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); @@ -75,7 +75,7 @@ pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ - pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); pci_write_config16(pmc, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 05dd134..fd69c0e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -70,7 +70,7 @@ reg_script_run(core_msr_script); /* * Enable ACPI PM timer emulation, which also lets microcode know - * location of ACPI_PMIO_BASE. This also enables other features + * location of ACPI_BASE_ADDRESS. This also enables other features * implemented in microcode. */ enable_pm_timer_emulation(); diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 0b52095..b01c806 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,14 +25,14 @@ #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) -#define ACPI_PMIO_BASE 0x400 -#define ACPI_PMIO_SIZE 0x100 +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 /* CST Range (R/W) IO port block size */ #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 /* ACPI PMIO Offset to C-state register*/ -#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14) +#define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 150f7ce..0519434 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -44,8 +44,8 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = ACPI_PMIO_BASE; - res->size = ACPI_PMIO_SIZE; + res->base = ACPI_BASE_ADDRESS; + res->size = ACPI_BASE_SIZE; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 9999913..3ceb066 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -101,8 +101,8 @@ static uint32_t reset_smi_status(void) { - uint32_t smi_sts = inl(ACPI_PMIO_BASE + SMI_STS); - outl(smi_sts, ACPI_PMIO_BASE + SMI_STS); + uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); + outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); return smi_sts; } @@ -116,8 +116,8 @@ * bit in the SMI status register. That makes things difficult for * determining if the power button caused an SMI. */ - if (sts == 0 && !(inl(ACPI_PMIO_BASE + PM1_CNT) & SCI_EN)) { - uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); + if (sts == 0 && !(inl(ACPI_BASE_ADDRESS + PM1_CNT) & SCI_EN)) { + uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) @@ -129,41 +129,41 @@ uint32_t get_smi_en(void) { - return inl(ACPI_PMIO_BASE + SMI_EN); + return inl(ACPI_BASE_ADDRESS + SMI_EN); } void enable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); smi_en |= mask; - outl(smi_en, ACPI_PMIO_BASE + SMI_EN); + outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } void disable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_PMIO_BASE + SMI_EN); + uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); smi_en &= ~mask; - outl(smi_en, ACPI_PMIO_BASE + SMI_EN); + outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } void enable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); pm1_cnt |= mask; - outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); } void disable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); + uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); pm1_cnt &= ~mask; - outl(pm1_cnt, ACPI_PMIO_BASE + PM1_CNT); + outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); } static uint16_t reset_pm1_status(void) { - uint16_t pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); - outw(pm1_sts, ACPI_PMIO_BASE + PM1_STS); + uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); return pm1_sts; } @@ -197,7 +197,7 @@ void enable_pm1(uint16_t events) { - outw(events, ACPI_PMIO_BASE + PM1_EN); + outw(events, ACPI_BASE_ADDRESS + PM1_EN); } static uint32_t print_tco_status(uint32_t tco_sts) @@ -219,10 +219,10 @@ static uint32_t reset_tco_status(void) { - uint32_t tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); - uint32_t tco_en = inl(ACPI_PMIO_BASE + TCO1_CNT); + uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - outl(tco_sts, ACPI_PMIO_BASE + TCO_STS); + outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS); return tco_sts & tco_en; } @@ -233,16 +233,16 @@ void enable_gpe(uint32_t mask) { - uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); gpe0a_en |= mask; - outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); + outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0)); } void disable_gpe(uint32_t mask) { - uint32_t gpe0a_en = inl(ACPI_PMIO_BASE + GPE0_EN(0)); + uint32_t gpe0a_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(0)); gpe0a_en &= ~mask; - outl(gpe0a_en, ACPI_PMIO_BASE + GPE0_EN(0)); + outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0_EN(0)); } void disable_all_gpe(void) @@ -256,15 +256,15 @@ int i; for (i = 1; i < GPE0_REG_MAX; i++) { - uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(i)); - outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(i)); + uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); + outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); } } static uint32_t reset_gpe_status(void) { - uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(0)); - outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(0)); + uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); + outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(0)); return gpe_sts; } @@ -324,9 +324,9 @@ if (stopwatch_expired(&sw)) return rc; - sts = inl(ACPI_PMIO_BASE + GPE0_STS(bank)); + sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); if (sts & mask) { - outl(mask, ACPI_PMIO_BASE + GPE0_STS(bank)); + outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); rc = 1; } } while (sts & mask); @@ -367,7 +367,7 @@ } /* Clear SLP_TYP. */ - outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_PMIO_BASE + PM1_CNT); + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } return prev_sleep_state; } @@ -389,8 +389,8 @@ return; for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); + ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); + ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } @@ -402,10 +402,10 @@ int i; uintptr_t pmc_bar0 = read_pmc_mmio_bar(); - ps->pm1_sts = inw(ACPI_PMIO_BASE + PM1_STS); - ps->pm1_en = inw(ACPI_PMIO_BASE + PM1_EN); - ps->pm1_cnt = inl(ACPI_PMIO_BASE + PM1_CNT); - ps->tco_sts = inl(ACPI_PMIO_BASE + TCO_STS); + ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2)); @@ -421,10 +421,10 @@ "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n", ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3); printk(BIOS_DEBUG, "smi_en: %08x smi_sts: %08x\n", - inl(ACPI_PMIO_BASE + SMI_EN), inl(ACPI_PMIO_BASE + SMI_STS)); + inl(ACPI_BASE_ADDRESS + SMI_EN), inl(ACPI_BASE_ADDRESS + SMI_STS)); for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_PMIO_BASE + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_PMIO_BASE + GPE0_EN(i)); + ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); + ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } @@ -434,10 +434,10 @@ int vboot_platform_is_resuming(void) { - if (!(inw(ACPI_PMIO_BASE + PM1_STS) & WAK_STS)) + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; - return acpi_sleep_from_pm1(inl(ACPI_PMIO_BASE + PM1_CNT)) == ACPI_S3; + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } /* @@ -480,7 +480,7 @@ */ void vboot_platform_prepare_reboot(void) { - const uint16_t port = ACPI_PMIO_BASE + PM1_CNT; + const uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT; outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port); } @@ -566,6 +566,6 @@ */ msr.hi = (3579545ULL << 32) / CTC_FREQ; /* Set PM1 timer IO port and enable*/ - msr.lo = EMULATE_PM_TMR_EN | (ACPI_PMIO_BASE + R_ACPI_PM1_TMR); + msr.lo = EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + R_ACPI_PM1_TMR); wrmsr(MSR_EMULATE_PM_TMR, msr); } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 87ba26b..9781b8f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -105,9 +105,9 @@ uint32_t reg; /* Stop TCO timer */ - reg = inl(ACPI_PMIO_BASE + TCO1_CNT); + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); reg |= TCO_TMR_HLT; - outl(reg, ACPI_PMIO_BASE + TCO1_CNT); + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); } static void migrate_power_state(int is_recovery) diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c index 549a914..88ea819 100644 --- a/src/soc/intel/common/smihandler.c +++ b/src/soc/intel/common/smihandler.c @@ -135,7 +135,7 @@ /* First, disable further SMIs */ disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); @@ -198,7 +198,7 @@ * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ - reg32 = inl(ACPI_PMIO_BASE + PM1_CNT); + reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); if (reg32 & SCI_EN) { /* The OS is not an ACPI OS, so we set the state to S0 */ disable_pm1_control(SLP_EN | SLP_TYP); -- To view, visit https://review.coreboot.org/20038 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a Gerrit-Change-Number: 20038 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init
by Barnali Sarkar (Code Review) 05 Jun '17

05 Jun '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20037 Change subject: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init ...................................................................... soc/intel/apollolake: Perform CPU MP Init before FSP-S Init As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=none BRANCH=none TEST=Build and boot Reef Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h 3 files changed, 32 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/20037/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 91bae2d..9f87248 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -147,7 +147,7 @@ .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = apollolake_init_cpus, + .init = DEVICE_NOOP, .scan_bus = NULL, .acpi_fill_ssdt_generator = generate_cpu_entries, }; diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index ff300bc..05dd134 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -16,6 +16,8 @@ * GNU General Public License for more details. */ +#include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> @@ -25,7 +27,9 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <fsp/api.h> #include <reg_script.h> +#include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> @@ -107,19 +111,21 @@ } /* - * Do essential initialization tasks before APs can be fired up + * Do essential initialization tasks before APs can be fired up - * - * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. + * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + * + * Do, FSP loading before MP Init to ensure that the FSP cmponent stored in + * external stage cache in TSEG does not flush off due to SMM relocation + * during MP Init stage. */ static void pre_mp_init(void) { - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - /* Make sure BSP is using the microcode from cbfs */ intel_update_microcode_from_cbfs(); + fsps_load(romstage_handoff_is_resume()); } /* Find CPU topology */ @@ -198,8 +204,11 @@ .post_mp_init = southbridge_smm_enable_smi, }; -void apollolake_init_cpus(device_t dev) +static void soc_init_cpus(void *unused) { + device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + assert(dev != NULL); + /* Clear for take-off */ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n"); @@ -209,3 +218,17 @@ mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); } + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void soc_post_cpus_init(void *unused) +{ + if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); + x86_mtrr_check(); +} + +/* + * Do CPU MP Init before FSP Silicon Init + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 0900eef..54fcf52 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -24,7 +24,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> -void apollolake_init_cpus(struct device *dev); void set_max_freq(void); void enable_untrusted_mode(void); #endif -- To view, visit https://review.coreboot.org/20037 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Gerrit-Change-Number: 20037 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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coreboot-gerrit June 2017