coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: address of riscv register is incorrect
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20043 ) Change subject: address of riscv register is incorrect ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54912/ : FAILURE -- To view, visit https://review.coreboot.org/20043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Gerrit-Change-Number: 20043 Gerrit-PatchSet: 4 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 10:29:26 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: address of riscv register is incorrect
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20043 ) Change subject: address of riscv register is incorrect ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54911/ : FAILURE -- To view, visit https://review.coreboot.org/20043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Gerrit-Change-Number: 20043 Gerrit-PatchSet: 3 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 10:28:15 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: address of riscv register is incorrect
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20043 ) Change subject: address of riscv register is incorrect ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54910/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10607/ : SUCCESS -- To view, visit https://review.coreboot.org/20043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Gerrit-Change-Number: 20043 Gerrit-PatchSet: 2 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 10:27:12 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
by Arthur Heymans (Code Review) 06 Jun '17

06 Jun '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20045 ) Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout ...................................................................... Patch Set 1: Code-Review+1 Is raminit that fast device are not ready at this stage? -- To view, visit https://review.coreboot.org/20045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Gerrit-Change-Number: 20045 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 10:23:55 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: address of riscv register is incorrect
by Anonymous Coward (Code Review) 06 Jun '17

06 Jun '17

Anonymous Coward #1001664 has removed build bot (Jenkins) from this change. ( https://review.coreboot.org/20047 ) Change subject: address of riscv register is incorrect ...................................................................... Removed reviewer build bot (Jenkins). -- To view, visit https://review.coreboot.org/20047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd Gerrit-Change-Number: 20047 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

1 0

Change in coreboot[master]: address of riscv register is incorrect
by Anonymous Coward (Code Review) 06 Jun '17

06 Jun '17

Anonymous Coward #1001664 has removed a vote on this change. Change subject: address of riscv register is incorrect ...................................................................... Removed Verified+1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/20047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteVote Gerrit-Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd Gerrit-Change-Number: 20047 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: address of riscv register is incorrect
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20047 ) Change subject: address of riscv register is incorrect ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10606/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54909/ : SUCCESS -- To view, visit https://review.coreboot.org/20047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd Gerrit-Change-Number: 20047 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 10:20:58 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: address of riscv register is incorrect
by Anonymous Coward (Code Review) 06 Jun '17

06 Jun '17

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20047 Change subject: address of riscv register is incorrect ...................................................................... address of riscv register is incorrect I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception[csrwi 0x320,7]. This is operate for mcounteren. This address is error. 0x306 is right. scounteren is not need to be set, because S-mode code controls it. Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd Signed-off-by: wxjstz <wxjstz(a)126.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/20047/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2c440d2..abb8b30 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -316,6 +316,5 @@ // Until we trust our toolchain use the hardcoded constants. // These were in flux and people who get the older toolchain // will have difficult-to-debug failures. - write_csr(/*mucounteren*/0x320, 7); - write_csr(/*mscounteren*/0x321, 7); + write_csr(/*mucounteren*/0x306, 7); } -- To view, visit https://review.coreboot.org/20047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib80faa5d9836fe13f964829928e9f07ca5cd3dbd Gerrit-Change-Number: 20047 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

1 0

Change in coreboot[master]: Simplify the code of riscv exception handling
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20046 ) Change subject: Simplify the code of riscv exception handling ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10605/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54908/ : SUCCESS -- To view, visit https://review.coreboot.org/20046 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I92f7df2202f1c886789a9a29285f4321eec75d23 Gerrit-Change-Number: 20046 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 09:53:38 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: Simplify the code of riscv exception handling
by Anonymous Coward (Code Review) 06 Jun '17

06 Jun '17

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20046 Change subject: Simplify the code of riscv exception handling ...................................................................... Simplify the code of riscv exception handling There is some useless code. This code is not necessary. It's cam be remove. The code will become simple and do not need to insert the assembly code Change-Id: I92f7df2202f1c886789a9a29285f4321eec75d23 Signed-off-by: wxjstz <wxjstz(a)126.com> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 4 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20046/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 4dd3d5b..0cfd8dc 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,6 @@ } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j supervisor_call_return"); } static const char *const exception_names[] = { @@ -206,6 +205,7 @@ case CAUSE_HYPERVISOR_ECALL: case CAUSE_MACHINE_ECALL: print_trap_information(tf); + die("Can't recover from trap. Halting.\n"); break; case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); @@ -225,10 +225,10 @@ printk(BIOS_EMERG, "Coreboot: can not handle a trap:\n"); printk(BIOS_EMERG, "================================\n"); print_trap_information(tf); + die("Can't recover from trap. Halting.\n"); break; } - die("Can't recover from trap. Halting.\n"); } static uint32_t fetch_instruction(uintptr_t vaddr) { @@ -262,7 +262,6 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); } void handle_misaligned_store(trapframe *tf) { @@ -290,5 +289,4 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index ae32379..7eb964e 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -105,17 +105,7 @@ .endm -.globl estack - .text - .global supervisor_trap_entry -supervisor_trap_entry: - csrw mscratch, sp - # load in the top of the machine stack - la sp, _estack - addi sp,sp,-MENTRY_FRAME_SIZE - save_tf - move a0,sp - jal trap_handler + .global trap_entry trap_entry: csrw mscratch, sp @@ -136,14 +126,7 @@ save_tf move a0,sp jal trap_handler - .global supervisor_call_return -supervisor_call_return: - csrr a0, mscratch - restore_regs - # go back into supervisor call - .word 0x30200073 # mret - .global machine_call_return -machine_call_return: + csrr a0, mscratch restore_regs # go back into machine call -- To view, visit https://review.coreboot.org/20046 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I92f7df2202f1c886789a9a29285f4321eec75d23 Gerrit-Change-Number: 20046 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017