coreboot-gerrit June 2017

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Change in coreboot[master]: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20037 ) Change subject: soc/intel/apollolake: Perform CPU MP Init before FSP-S Init ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10619/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54927/ : SUCCESS -- To view, visit https://review.coreboot.org/20037 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49f336c10d6afb71f3a3b0cb8423c7fa94b6d595 Gerrit-Change-Number: 20037 Gerrit-PatchSet: 2 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:41:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove setting flex_ratio to TDP nominal
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20050 ) Change subject: soc/intel/skylake: Remove setting flex_ratio to TDP nominal ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54932/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10624/ : SUCCESS -- To view, visit https://review.coreboot.org/20050 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Gerrit-Change-Number: 20050 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:40:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common library code
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: Use CPU common library code ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54931/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10623/ : SUCCESS -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-Change-Number: 19827 Gerrit-PatchSet: 8 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:39:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove setting flex_ratio to TDP nominal
by Barnali Sarkar (Code Review) 06 Jun '17

06 Jun '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20050 Change subject: soc/intel/skylake: Remove setting flex_ratio to TDP nominal ...................................................................... soc/intel/skylake: Remove setting flex_ratio to TDP nominal Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured in MSR_PLATFORM_INFO(0xCE). If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done using MSR_FLEX_RATIO (0x194). Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is actually less than the factory configured Maximum Non TURBO Ratio (P1). So, this code is actually not required. Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor. This Bit implies Processor Boot Max Frequency - 0 = Disable Boot Max Frequency 1 = Enable Boot Max Frequency (Default) This setting determines if the processor will operate at maximum frequency at power-on and boot. Thus this patch will avoid one extra platform warm reset now onwards. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/skylake/bootblock/cpu.c 1 file changed, 0 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20050/1 diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6963b82..78b93ad 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -27,68 +27,9 @@ #include <soc/pci_devs.h> #include <stdint.h> -/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */ -#define SPI_STRAP_MAX_FREQ (1<<12) -/* Soft Reset Data Register Bit 6-11 = Flex Ratio */ -#define FLEX_RATIO_BIT 6 - -static void set_pch_cpu_strap(u8 flex_ratio) -{ - u32 soft_reset_data; - - /* Soft Reset Data Register Bit 12 = MAX Boot Frequency - * Bit 6-11 = Flex Ratio - * Soft Reset Data register located at SPIBAR0 offset 0xF8[0:15]. - */ - soft_reset_data = SPI_STRAP_MAX_FREQ; - soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT); - fast_spi_set_strap_msg_data(soft_reset_data); -} - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set PCH Soft Reset Data Register with new Flex Ratio */ - set_pch_cpu_strap(nominal_ratio); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue soft reset, will be "CPU only" due to soft reset data */ - soft_reset(); -} - void bootblock_cpu_init(void) { fast_spi_cache_bios_region(); - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); intel_update_microcode_from_cbfs(); } -- To view, visit https://review.coreboot.org/20050 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Gerrit-Change-Number: 20050 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Moved update microcode from cbfs to pre_m...
by Barnali Sarkar (Code Review) 06 Jun '17

06 Jun '17

Barnali Sarkar has uploaded this change for review. ( https://review.coreboot.org/20051 Change subject: soc/intel/skylake: Moved update microcode from cbfs to pre_mp_init ...................................................................... soc/intel/skylake: Moved update microcode from cbfs to pre_mp_init FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in pre_mp_init callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/cpu.c 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20051/1 diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 78b93ad..6e21945 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -30,7 +30,6 @@ void bootblock_cpu_init(void) { fast_spi_cache_bios_region(); - intel_update_microcode_from_cbfs(); } void set_max_freq(void) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 95d9ad9..2afb073 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -457,6 +457,12 @@ .id_table = cpu_table, }; +static void pre_mp_init(void) +{ + intel_update_microcode_from_cbfs(); + soc_fsp_load(); +} + static int get_cpu_count(void) { msr_t msr; @@ -532,7 +538,7 @@ * that are set prior to ramstage. * Real MTRRs programming are being done after resource allocation. */ - .pre_mp_init = soc_fsp_load, + .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, -- To view, visit https://review.coreboot.org/20051 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5606563726c00974f00285acfa435cadc90a085e Gerrit-Change-Number: 20051 Gerrit-PatchSet: 1 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Advertise correct frequency
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19995 ) Change subject: nb/intel/sandybridge/raminit: Advertise correct frequency ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54926/ : SUCCESS -- To view, visit https://review.coreboot.org/19995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Gerrit-Change-Number: 19995 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:33:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20045 ) Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10618/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54925/ : SUCCESS -- To view, visit https://review.coreboot.org/20045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Gerrit-Change-Number: 20045 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:26:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/model_206ax: Use tsc monotonic timer
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20044 ) Change subject: cpu/intel/model_206ax: Use tsc monotonic timer ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10617/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54924/ : SUCCESS -- To view, visit https://review.coreboot.org/20044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Gerrit-Change-Number: 20044 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:24:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/pcie: Disable unused bridges
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19819 ) Change subject: nb/intel/sandybridge/pcie: Disable unused bridges ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10616/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54923/ : SUCCESS -- To view, visit https://review.coreboot.org/19819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537 Gerrit-Change-Number: 19819 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 13:23:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
by Patrick Rudolph (Code Review) 06 Jun '17

06 Jun '17

Hello Arthur Heymans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20045 to look at the new patch set (#4). Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout ...................................................................... sb/intel/bd82x6x/pcie: Add PCIe reset timeout If no device is found, make sure to wait 100msec and scan bridge again. May introduce a boot delay of up to 100msec. As timestamps are used the delay is at maximum 100msec, no matter how many PCIe ports are there. The delay is only used in case no device is found. If a device has been found there's no need to wait. Fixes a regression introduced by Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 where a port is disabled as the connected device hasn't powered up yet. Tested on Lenovo T430. Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20045/4 -- To view, visit https://review.coreboot.org/20045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Gerrit-Change-Number: 20045 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2017