coreboot-gerrit June 2017

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Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20045 ) Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54907/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10604/ : SUCCESS -- To view, visit https://review.coreboot.org/20045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Gerrit-Change-Number: 20045 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 09:43:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/model_206ax: Use tsc monotonic timer
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20044 ) Change subject: cpu/intel/model_206ax: Use tsc monotonic timer ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54906/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10603/ : SUCCESS -- To view, visit https://review.coreboot.org/20044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Gerrit-Change-Number: 20044 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 09:23:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/pcie: Disable unused bridges
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19819 ) Change subject: nb/intel/sandybridge/pcie: Disable unused bridges ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54905/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10602/ : SUCCESS -- To view, visit https://review.coreboot.org/19819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537 Gerrit-Change-Number: 19819 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 09:17:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/pcie: Add PCIe reset timeout
by Patrick Rudolph (Code Review) 06 Jun '17

06 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20045 Change subject: sb/intel/bd82x6x/pcie: Add PCIe reset timeout ...................................................................... sb/intel/bd82x6x/pcie: Add PCIe reset timeout If no device is found, make sure to wait 100msec and scan bridge again. May introduce a boot delay of up to 100msec. As timestamps are used the delay is at maximum 100msec, no matter how many PCIe ports are there. The delay is only used in case no device is found. If a device has been found there's no need to wait. Fixes a regression introduced by Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 where a port is disabled as the connected device hasn't powered up yet. Tested on Lenovo T430. Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20045/1 diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 627b6f7..939890b 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -20,7 +20,12 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> +#include <timestamp.h> +#include <delay.h> #include "pch.h" + +static uint64_t ts_pcie_init = 0; +#define PCIE_RESET_DELAY 100000ULL static void pch_pcie_pm_early(struct device *dev) { @@ -267,6 +272,8 @@ { /* Power Management init before enumeration */ pch_pcie_pm_early(dev); + /* Store time-stamp for PCIe reset timeout */ + ts_pcie_init = MAX(timestamp_get(), ts_pcie_init); } static void pch_pcie_disable(device_t dev) @@ -279,11 +286,28 @@ static void pch_pciexp_scan_bridge(device_t dev) { + uint64_t delay; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ pciexp_scan_bridge(dev); + /* + * No device found ? + * Respect PCIe 1.0 Spec and wait at least 100msec after reset. + */ + delay = (timestamp_get() - ts_pcie_init) / timestamp_tick_freq_mhz(); + if (!dev_is_active_bridge(dev) && (delay < PCIE_RESET_DELAY)) { + delay = PCIE_RESET_DELAY - delay; + printk(BIOS_DEBUG, "%s: Waiting additional %lld usec\n", + dev_path(dev), delay); + + udelay(delay); + + /* Scan again */ + pciexp_scan_bridge(dev); + } + if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } else { -- To view, visit https://review.coreboot.org/20045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I990e2577f0acf7d1956b42af2611405f1421e6d3 Gerrit-Change-Number: 20045 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: cpu/intel/model_206ax: Use tsc monotonic timer
by Patrick Rudolph (Code Review) 06 Jun '17

06 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20044 Change subject: cpu/intel/model_206ax: Use tsc monotonic timer ...................................................................... cpu/intel/model_206ax: Use tsc monotonic timer Switch from lapic to tsc. Allows timestamps to be used in coreboot, as there's a reference clock available to calculate correct time units. Tested on Lenovo T430. Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc A src/cpu/intel/model_206ax/tsc_freq.c 3 files changed, 34 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20044/1 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 6c04fba..1415111 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,14 +12,15 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select HAVE_MONOTONIC_TIMER select SMP select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE - select LAPIC_MONOTONIC_TIMER select CPU_INTEL_COMMON config BOOTBLOCK_CPU_INIT diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index b79ccd7..7516e9d 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,6 +5,10 @@ ramstage-y += acpi.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin diff --git a/src/cpu/intel/model_206ax/tsc_freq.c b/src/cpu/intel/model_206ax/tsc_freq.c new file mode 100644 index 0000000..545ca5f --- /dev/null +++ b/src/cpu/intel/model_206ax/tsc_freq.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "model_206ax.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); +} -- To view, visit https://review.coreboot.org/20044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1 Gerrit-Change-Number: 20044 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: address of riscv register is incorrect
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20043 ) Change subject: address of riscv register is incorrect ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10601/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54904/ : SUCCESS -- To view, visit https://review.coreboot.org/20043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Gerrit-Change-Number: 20043 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 08:58:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: address of riscv register is incorrect
by Anonymous Coward (Code Review) 06 Jun '17

06 Jun '17

Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20043 Change subject: address of riscv register is incorrect ...................................................................... address of riscv register is incorrect I triggered a bug, when I try to debug riscv code by spike. This bug is caused by an instruction exception. This instruction is [csrwi 0x320,7]. Through this I found the register address wrong Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a signed-off-by: wxjstz<wxjstz(a)126.com> Signed-off-by: wxjstz <wxjstz(a)126.com> --- M src/arch/riscv/virtual_memory.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20043/1 diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 2c440d2..9ab7548 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -316,6 +316,6 @@ // Until we trust our toolchain use the hardcoded constants. // These were in flux and people who get the older toolchain // will have difficult-to-debug failures. - write_csr(/*mucounteren*/0x320, 7); - write_csr(/*mscounteren*/0x321, 7); + write_csr(/*mcounteren*/0x306, 7); + write_csr(/*scounteren*/0x106, 7); } -- To view, visit https://review.coreboot.org/20043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a Gerrit-Change-Number: 20043 Gerrit-PatchSet: 1 Gerrit-Owner: Anonymous Coward #1001664

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Change in coreboot[master]: drivers/i2c/ck505: Add generic driver to configure clockgen
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20042 ) Change subject: drivers/i2c/ck505: Add generic driver to configure clockgen ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10600/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54903/ : SUCCESS -- To view, visit https://review.coreboot.org/20042 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Gerrit-Change-Number: 20042 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 08:09:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: Update UF camera i2c address
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20023 ) Change subject: mb/google/soraka: Update UF camera i2c address ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54902/ : SUCCESS -- To view, visit https://review.coreboot.org/20023 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b Gerrit-Change-Number: 20023 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 08:00:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/i2c/ck505: Add generic driver to configure clockgen
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20042 ) Change subject: drivers/i2c/ck505: Add generic driver to configure clockgen ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54901/ : UNSTABLE -- To view, visit https://review.coreboot.org/20042 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Gerrit-Change-Number: 20042 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 07:59:23 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017