coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: payloads: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 28 Jun '17

28 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20396 ) Change subject: payloads: Add whitespace around '<<' ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56362/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11960/ : SUCCESS -- To view, visit https://review.coreboot.org/20396 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042 Gerrit-Change-Number: 20396 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 22:52:18 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: northbridge/amd/agesa/*: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20399 ) Change subject: northbridge/amd/agesa/*: Add whitespace around '<<' ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56367/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11959/ : SUCCESS -- To view, visit https://review.coreboot.org/20399 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 Gerrit-Change-Number: 20399 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 21:34:37 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: northbridge/intel: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge/intel: Add whitespace around '<<' ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56366/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/11958/ : SUCCESS -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 21:16:57 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: northbridge/amd/agesa/*: Add whitespace around '<<'
by HAOUAS Elyes (Code Review) 27 Jun '17

27 Jun '17

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/20399 Change subject: northbridge/amd/agesa/*: Add whitespace around '<<' ...................................................................... northbridge/amd/agesa/*: Add whitespace around '<<' Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family10/northbridge.c M src/northbridge/amd/agesa/family10/reset_test.h M src/northbridge/amd/agesa/family12/amdfam12_conf.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/amdfam14_conf.c M src/northbridge/amd/agesa/family15/northbridge.c M src/northbridge/amd/agesa/family15rl/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 9 files changed, 59 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/20399/1 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6f7a053..15693b7 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -63,14 +63,14 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -82,12 +82,12 @@ if ((segbusn & 0xff)>(0xe0-1)) {// use next segn u32 segn = (segbusn >> 8) & 0x0f; segn++; - segbusn = segn<<8; + segbusn = segn << 8; } if (segbusn>>8) { u32 val; val = pci_read_config32(dev, 0x160); - val &= ~(0xf<<25); + val &= ~(0xf << 25); val |= (segbusn & 0xf00)<<(25-8); pci_write_config32(dev, 0x160, val); } @@ -135,9 +135,9 @@ index = (reg-0xc0)>>3; val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num<(index+1)) sysconf.io_addr_num = index+1; @@ -166,11 +166,11 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -181,7 +181,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -267,7 +267,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); @@ -329,7 +329,7 @@ if (!reg) { //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -366,7 +366,7 @@ // but we need one index to differ them. so same node and // same link can have multi range u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -669,7 +669,7 @@ hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } @@ -936,7 +936,7 @@ nb_cfg_54 = 0; ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); if (ApicIdCoreIdSize) { - siblings = (1<<ApicIdCoreIdSize)-1; + siblings = (1 << ApicIdCoreIdSize)-1; } else { siblings = 3; //quad core } diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 48634ea..61de4d9 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -23,9 +23,9 @@ #define NODE_ID 0x60 #define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) static inline u32 warm_reset_detect(u8 nodeid) { diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 46af104..4c5ef19 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -53,12 +53,12 @@ device_t dev; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -98,10 +98,10 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? pci_write_config32(__f1_dev[0], reg, tempreg); } @@ -111,7 +111,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); pci_write_config32(__f1_dev[0], reg, tempreg); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c931bf0..206ae47 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -108,7 +108,7 @@ u32 val; printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); @@ -162,7 +162,7 @@ if (!reg) { //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -198,7 +198,7 @@ // but we need one index to differ them. so same node and // same link can have multi range u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -280,7 +280,7 @@ if (d.mask & 1) { hole = pci_read_config32(__f1_dev[0], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole } } diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 0e588ad..5de7a05 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -53,12 +53,12 @@ device_t dev; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -98,10 +98,10 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? pci_write_config32(__f1_dev[0], reg, tempreg); } @@ -111,7 +111,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); pci_write_config32(__f1_dev[0], reg, tempreg); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5cb0f91..15af024 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -67,12 +67,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -82,10 +82,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -95,7 +95,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -174,7 +174,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -668,7 +668,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index aa24a6a..8cb801b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -66,12 +66,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -81,10 +81,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -94,7 +94,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -173,7 +173,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -664,7 +664,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 95787fc..66da338 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -65,12 +65,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -80,10 +80,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -93,7 +93,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -172,7 +172,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -663,7 +663,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index f91448a..4545601 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -65,12 +65,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -80,10 +80,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -93,7 +93,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -172,7 +172,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -678,7 +678,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } -- To view, visit https://review.coreboot.org/20399 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 Gerrit-Change-Number: 20399 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: northbridge/intel: Add whitespace around '<<'
by HAOUAS Elyes (Code Review) 27 Jun '17

27 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20398 to look at the new patch set (#2). Change subject: northbridge/intel: Add whitespace around '<<' ...................................................................... northbridge/intel: Add whitespace around '<<' Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i3100/memory_initialized.c M src/northbridge/intel/i3100/pciexp_porta.c M src/northbridge/intel/i3100/pciexp_porta_ep80579.c M src/northbridge/intel/i3100/raminit.c M src/northbridge/intel/i3100/raminit_ep80579.c M src/northbridge/intel/i82830/memory_initialized.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/x4x/raminit_ddr2.c M src/northbridge/intel/x4x/x4x.h 18 files changed, 168 insertions(+), 168 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20398/2 -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: northbridge: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge: Add whitespace around '<<' ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56365/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/11957/ : SUCCESS -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 21:12:05 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: northbridge: Add whitespace around '<<'
by HAOUAS Elyes (Code Review) 27 Jun '17

27 Jun '17

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/20398 Change subject: northbridge: Add whitespace around '<<' ...................................................................... northbridge: Add whitespace around '<<' Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family10/northbridge.c M src/northbridge/amd/agesa/family10/reset_test.h M src/northbridge/amd/agesa/family12/amdfam12_conf.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/amdfam14_conf.c M src/northbridge/amd/agesa/family15/northbridge.c M src/northbridge/amd/agesa/family15rl/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/early_ht.c M src/northbridge/amd/amdfam10/get_pci1234.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/misc_control.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/pci.c M src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c M src/northbridge/amd/amdht/comlib.c M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/coherent_ht.c M src/northbridge/amd/amdk8/f.h M src/northbridge/amd/amdk8/f_pci.c M src/northbridge/amd/amdk8/incoherent_ht.c M src/northbridge/amd/amdk8/misc_control.c M src/northbridge/amd/amdk8/northbridge.c M src/northbridge/amd/amdk8/pre_f.h M src/northbridge/amd/amdk8/raminit.c M src/northbridge/amd/amdk8/raminit_f.c M src/northbridge/amd/amdk8/raminit_f_dqs.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d_gcc.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct/mctecc_d.c M src/northbridge/amd/amdmct/mct/mctgr.c M src/northbridge/amd/amdmct/mct/mcthdi.c M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct/mctpro_d.c M src/northbridge/amd/amdmct/mct/mctsrc.c M src/northbridge/amd/amdmct/mct/mctsrc2p.c M src/northbridge/amd/amdmct/mct/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c M src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c M src/northbridge/amd/amdmct/mct_ddr3/mctwl.c M src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00670F00/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i3100/memory_initialized.c M src/northbridge/intel/i3100/pciexp_porta.c M src/northbridge/intel/i3100/pciexp_porta_ep80579.c M src/northbridge/intel/i3100/raminit.c M src/northbridge/intel/i3100/raminit_ep80579.c M src/northbridge/intel/i82830/memory_initialized.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/x4x/raminit_ddr2.c M src/northbridge/intel/x4x/x4x.h 77 files changed, 742 insertions(+), 742 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20398/1 diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6f7a053..15693b7 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -63,14 +63,14 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -82,12 +82,12 @@ if ((segbusn & 0xff)>(0xe0-1)) {// use next segn u32 segn = (segbusn >> 8) & 0x0f; segn++; - segbusn = segn<<8; + segbusn = segn << 8; } if (segbusn>>8) { u32 val; val = pci_read_config32(dev, 0x160); - val &= ~(0xf<<25); + val &= ~(0xf << 25); val |= (segbusn & 0xf00)<<(25-8); pci_write_config32(dev, 0x160, val); } @@ -135,9 +135,9 @@ index = (reg-0xc0)>>3; val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num<(index+1)) sysconf.io_addr_num = index+1; @@ -166,11 +166,11 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -181,7 +181,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -267,7 +267,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); @@ -329,7 +329,7 @@ if (!reg) { //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -366,7 +366,7 @@ // but we need one index to differ them. so same node and // same link can have multi range u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -669,7 +669,7 @@ hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } @@ -936,7 +936,7 @@ nb_cfg_54 = 0; ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); if (ApicIdCoreIdSize) { - siblings = (1<<ApicIdCoreIdSize)-1; + siblings = (1 << ApicIdCoreIdSize)-1; } else { siblings = 3; //quad core } diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 48634ea..61de4d9 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -23,9 +23,9 @@ #define NODE_ID 0x60 #define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) static inline u32 warm_reset_detect(u8 nodeid) { diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 46af104..4c5ef19 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -53,12 +53,12 @@ device_t dev; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -98,10 +98,10 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? pci_write_config32(__f1_dev[0], reg, tempreg); } @@ -111,7 +111,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); pci_write_config32(__f1_dev[0], reg, tempreg); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c931bf0..206ae47 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -108,7 +108,7 @@ u32 val; printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); @@ -162,7 +162,7 @@ if (!reg) { //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -198,7 +198,7 @@ // but we need one index to differ them. so same node and // same link can have multi range u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -280,7 +280,7 @@ if (d.mask & 1) { hole = pci_read_config32(__f1_dev[0], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole } } diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 0e588ad..5de7a05 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -53,12 +53,12 @@ device_t dev; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -98,10 +98,10 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? pci_write_config32(__f1_dev[0], reg, tempreg); } @@ -111,7 +111,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); pci_write_config32(__f1_dev[0], reg, tempreg); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5cb0f91..15af024 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -67,12 +67,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -82,10 +82,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -95,7 +95,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -174,7 +174,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -668,7 +668,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index aa24a6a..8cb801b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -66,12 +66,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -81,10 +81,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -94,7 +94,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -173,7 +173,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -664,7 +664,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 95787fc..66da338 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -65,12 +65,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -80,10 +80,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -93,7 +93,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -172,7 +172,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -663,7 +663,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index f91448a..4545601 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -65,12 +65,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -80,10 +80,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -93,7 +93,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -172,7 +172,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -678,7 +678,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 611291a..7882da6 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -33,9 +33,9 @@ #define NODE_ID 0x60 #define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) /* Definitions of various FAM10 registers */ /* Function 0 */ @@ -95,8 +95,8 @@ #define DC_Twrwr3_2_MASK 3 #define DC_Trdrd3_2_SHIFT 12 /*DDR3 */ #define DC_Trdrd3_2_MASK 3 -#define DC_AltVidC3MemClkTriEn (1<<16) -#define DC_DqsRcvEnTrain (1<<18) +#define DC_AltVidC3MemClkTriEn (1 << 16) +#define DC_DqsRcvEnTrain (1 << 18) #define DC_MaxRdLatency_SHIFT 22 #define DC_MaxRdLatency_MASK 0x3ff @@ -107,14 +107,14 @@ #define DI_MrsBank_MASK 7 #define DI_MrsChipSel_SHIFT 20 #define DI_MrsChipSel_MASK 7 -#define DI_SendRchgAll (1<<24) -#define DI_SendAutoRefresh (1<<25) -#define DI_SendMrsCmd (1<<26) -#define DI_DeassertMemRstX (1<<27) -#define DI_AssertCke (1<<28) -#define DI_SendZQCmd (1<<29) /*DDR3 */ -#define DI_EnMrsCmd (1<<30) -#define DI_EnDramInit (1<<31) +#define DI_SendRchgAll (1 << 24) +#define DI_SendAutoRefresh (1 << 25) +#define DI_SendMrsCmd (1 << 26) +#define DI_DeassertMemRstX (1 << 27) +#define DI_AssertCke (1 << 28) +#define DI_SendZQCmd (1 << 29) /*DDR3 */ +#define DI_EnMrsCmd (1 << 30) +#define DI_EnDramInit (1 << 31) #define DRAM_MRS 0x84 #define DM_BurstCtrl_SHIFT 0 @@ -130,15 +130,15 @@ #define DM_DramTerm_MASK 7 #define DM_DramTermDyn_SHIFT 10 /* DDR3 */ #define DM_DramTermDyn_MASK 3 -#define DM_Ooff (1<<13) -#define DM_ASR (1<<18) -#define DM_SRT (1<<19) +#define DM_Ooff (1 << 13) +#define DM_ASR (1 << 18) +#define DM_SRT (1 << 19) #define DM_Tcwl_SHIFT 20 #define DM_Tcwl_MASK 7 -#define DM_PchgPDModeSel (1<<23) /* DDR3 */ +#define DM_PchgPDModeSel (1 << 23) /* DDR3 */ #define DM_MPrLoc_SHIFT 24 /* DDR3 */ #define DM_MPrLoc_MASK 3 -#define DM_MprEn (1<<26) /* DDR3 */ +#define DM_MprEn (1 << 26) /* DDR3 */ #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 @@ -223,7 +223,7 @@ #define DTH_TREF_MASK 3 #define DTH_TREF_7_8_US 2 #define DTH_TREF_3_9_US 3 -#define DTH_DisAutoRefresh (1<<18) +#define DTH_DisAutoRefresh (1 << 18) #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ #define DTH_TRFC_MASK 7 #define DTH_TRFC_75_256M 0 @@ -236,8 +236,8 @@ #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ #define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) -#define DCL_ExitSelfRef (1<<1) +#define DCL_InitDram (1 << 0) +#define DCL_ExitSelfRef (1 << 1) #define DCL_PllLockTime_SHIFT 2 #define DCL_PllLockTime_MASK 3 #define DCL_PllLockTime_15US 0 @@ -248,25 +248,25 @@ #define DCL_DramTerm_75_OH 1 #define DCL_DramTerm_150_OH 2 #define DCL_DramTerm_50_OH 3 -#define DCL_DisDqsBar (1<<6) /* only for DDR2 */ -#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */ -#define DCL_ParEn (1<<8) -#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */ -#define DCL_BurstLength32 (1<<10) /* only for DDR3 */ -#define DCL_Width128 (1<<11) +#define DCL_DisDqsBar (1 << 6) /* only for DDR2 */ +#define DCL_DramDrvWeak (1 << 7) /* only for DDR2 */ +#define DCL_ParEn (1 << 8) +#define DCL_SelfRefRateEn (1 << 9) /* only for DDR2 */ +#define DCL_BurstLength32 (1 << 10) /* only for DDR3 */ +#define DCL_Width128 (1 << 11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) -#define DCL_EnPhyDqsRcvEnTr (1<<18) -#define DCL_DimmEccEn (1<<19) -#define DCL_DynPageCloseEn (1<<20) +#define DCL_UnBuffDimm (1 << 16) +#define DCL_EnPhyDqsRcvEnTr (1 << 18) +#define DCL_DimmEccEn (1 << 19) +#define DCL_DynPageCloseEn (1 << 20) #define DCL_IdleCycInit_SHIFT 21 #define DCL_IdleCycInit_MASK 3 #define DCL_IdleCycInit_16CLK 0 #define DCL_IdleCycInit_32CLK 1 #define DCL_IdleCycInit_64CLK 2 #define DCL_IdleCycInit_96CLK 3 -#define DCL_ForceAutoPchg (1<<23) +#define DCL_ForceAutoPchg (1 << 23) #define DRAM_CONFIG_HIGH 0x94 #define DCH_MemClkFreq_SHIFT 0 @@ -278,27 +278,27 @@ #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */ #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */ #define DCH_MemClkFreq_800MHz 6 /* DDR 3 */ -#define DCH_MemClkFreqVal (1<<3) -#define DCH_Ddr3Mode (1<<8) -#define DCH_LegacyBiosMode (1<<9) +#define DCH_MemClkFreqVal (1 << 3) +#define DCH_Ddr3Mode (1 << 8) +#define DCH_LegacyBiosMode (1 << 9) #define DCH_ZqcsInterval_SHIFT 10 #define DCH_ZqcsInterval_MASK 3 #define DCH_ZqcsInterval_DIS 0 #define DCH_ZqcsInterval_64MS 1 #define DCH_ZqcsInterval_128MS 2 #define DCH_ZqcsInterval_256MS 3 -#define DCH_RDqsEn (1<<12) /* only for DDR2 */ -#define DCH_DisSimulRdWr (1<<13) -#define DCH_DisDramInterface (1<<14) -#define DCH_PowerDownEn (1<<15) +#define DCH_RDqsEn (1 << 12) /* only for DDR2 */ +#define DCH_DisSimulRdWr (1 << 13) +#define DCH_DisDramInterface (1 << 14) +#define DCH_PowerDownEn (1 << 15) #define DCH_PowerDownMode_SHIFT 16 #define DCH_PowerDownMode_MASK 1 #define DCH_PowerDownMode_Channel_CKE 0 #define DCH_PowerDownMode_ChipSelect_CKE 1 -#define DCH_FourRankSODimm (1<<17) -#define DCH_FourRankRDimm (1<<18) -#define DCH_SlowAccessMode (1<<20) -#define DCH_BankSwizzleMode (1<<22) +#define DCH_FourRankSODimm (1 << 17) +#define DCH_FourRankRDimm (1 << 18) +#define DCH_SlowAccessMode (1 << 20) +#define DCH_BankSwizzleMode (1 << 22) #define DCH_DcqBypassMax_SHIFT 24 #define DCH_DcqBypassMax_MASK 0xf #define DCH_DcqBypassMax_BASE 0 @@ -318,8 +318,8 @@ #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 #define DCAO_DctOffset_MASK 0x3fffffff -#define DCAO_DctAccessWrite (1<<30) -#define DCAO_DctAccessDone (1<<31) +#define DCAO_DctAccessWrite (1 << 30) +#define DCAO_DctAccessDone (1 << 31) #define DRAM_CTRL_ADDI_DATA_PORT 0x9c @@ -414,19 +414,19 @@ #define DACTC_CkeFineDelay_BASE 0 #define DACTC_CkeFineDelay_MIN 0 #define DACTC_CkeFineDelay_MAX 31 -#define DACTC_CkeSetup (1<<5) +#define DACTC_CkeSetup (1 << 5) #define DACTC_CsOdtFineDelay_SHIFT 8 #define DACTC_CsOdtFineDelay_MASK 0x1f #define DACTC_CsOdtFineDelay_BASE 0 #define DACTC_CsOdtFineDelay_MIN 0 #define DACTC_CsOdtFineDelay_MAX 31 -#define DACTC_CsOdtSetup (1<<13) +#define DACTC_CsOdtSetup (1 << 13) #define DACTC_AddrCmdFineDelay_SHIFT 16 #define DACTC_AddrCmdFineDelay_MASK 0x1f #define DACTC_AddrCmdFineDelay_BASE 0 #define DACTC_AddrCmdFineDelay_MIN 0 #define DACTC_AddrCmdFineDelay_MAX 31 -#define DACTC_AddrCmdSetup (1<<21) +#define DACTC_AddrCmdSetup (1 << 21) #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 #define DRDTC_RdDqsTimeByte0_SHIFT 0 @@ -448,17 +448,17 @@ #define DRDETC_RdDqsTimeCheck_SHIFT 0 #define DRAM_PHY_CTRL 0x08 -#define DPC_WrtLvTrEn (1<<0) -#define DPC_WrtLvTrMode (1<<1) -#define DPC_TrNibbleSel (1<<2) +#define DPC_WrtLvTrEn (1 << 0) +#define DPC_WrtLvTrMode (1 << 1) +#define DPC_TrNibbleSel (1 << 2) #define DPC_TrDimmSel_SHIFT 4 #define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ #define DPC_WrLvOdt_SHIFT 8 #define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ -#define DPC_WrLvODtEn (1<<12) -#define DPC_DqsRcvTrEn (1<<13) -#define DPC_DisAutoComp (1<<30) -#define DPC_AsyncCompUpdate (1<<31) +#define DPC_WrLvODtEn (1 << 12) +#define DPC_DqsRcvTrEn (1 << 13) +#define DPC_DisAutoComp (1 << 30) +#define DPC_AsyncCompUpdate (1 << 31) #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0 @@ -564,8 +564,8 @@ #define DWLE_WrLvErr_MASK 0xff #define DRAM_CTRL_MISC 0xa0 -#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */ -#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */ +#define DCM_MemCleared (1 << 0) /* RD == F2x110 [MemCleared] */ +#define DCM_DramEnabled (1 << 9) /* RD == F2x110 [DramEnabled] */ #define NB_TIME_STAMP_COUNT_LOW 0xb0 #define TscLow_SHIFT 0 @@ -578,24 +578,24 @@ #define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/ #define DDC_DllAdjust_SHIFT 0 #define DDC_DllAdjust_MASK 0xff -#define DDC_DllSlower (1<<8) -#define DDC_DllFaster (1<<9) +#define DDC_DllSlower (1 << 8) +#define DDC_DllFaster (1 << 9) #define DDC_WrtDqsAdjust_SHIFT 16 #define DDC_WrtDqsAdjust_MASK 0x7 -#define DDC_WrtDqsAdjustEn (1<<19) +#define DDC_WrtDqsAdjustEn (1 << 19) #define DRAM_CTRL_SEL_LOW 0x110 -#define DCSL_DctSelHiRngEn (1<<0) -#define DCSL_DctSelHi (1<<1) -#define DCSL_DctSelIntLvEn (1<<2) -#define DCSL_MemClrInit (1<<3) /* WR only */ -#define DCSL_DctGangEn (1<<4) -#define DCSL_DctDataIntLv (1<<5) +#define DCSL_DctSelHiRngEn (1 << 0) +#define DCSL_DctSelHi (1 << 1) +#define DCSL_DctSelIntLvEn (1 << 2) +#define DCSL_MemClrInit (1 << 3) /* WR only */ +#define DCSL_DctGangEn (1 << 4) +#define DCSL_DctDataIntLv (1 << 5) #define DCSL_DctSelIntLvAddr_SHIFT #define DCSL_DctSelIntLvAddr_MASK 3 -#define DCSL_DramEnable (1<<8) /* RD only */ -#define DCSL_MemClrBusy (1<<9) /* RD only */ -#define DCSL_MemCleared (1<<10) /* RD only */ +#define DCSL_DramEnable (1 << 8) /* RD only */ +#define DCSL_MemClrBusy (1 << 9) /* RD only */ +#define DCSL_MemCleared (1 << 10) /* RD only */ #define DCSL_DctSelBaseAddr_47_27_SHIFT 11 #define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff @@ -604,8 +604,8 @@ #define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff #define MEM_CTRL_CONF_LOW 0x118 -#define MCCL_MctPriCpuRd (1<<0) -#define MCCL_MctPriCpuWr (1<<1) +#define MCCL_MctPriCpuRd (1 << 0) +#define MCCL_MctPriCpuWr (1 << 1) #define MCCL_MctPriIsocRd_SHIFT 4 #define MCCL_MctPriIsoc_MASK 0x3 #define MCCL_MctPriIsocWr_SHIFT 6 @@ -634,10 +634,10 @@ #define MCCH_MctWrLimit_MASK 0x1f #define MCCH_MctPrefReqLimit_SHIFT 7 #define MCCH_MctPrefReqLimit_MASK 0x1f -#define MCCH_PrefCpuDis (1<<12) -#define MCCH_PrefIoDis (1<<13) -#define MCCH_PrefIoFixStrideEn (1<<14) -#define MCCH_PrefFixStrideEn (1<<15) +#define MCCH_PrefCpuDis (1 << 12) +#define MCCH_PrefIoDis (1 << 13) +#define MCCH_PrefIoFixStrideEn (1 << 14) +#define MCCH_PrefFixStrideEn (1 << 15) #define MCCH_PrefFixDist_SHIFT 16 #define MCCH_PrefFixDist_MASK 0x3 #define MCCH_PrefConfSat_SHIFT 18 @@ -648,78 +648,78 @@ #define MCCH_PrefTwoConf_MASK 0x7 #define MCCH_PrefThreeConf_SHIFT 25 #define MCCH_prefThreeConf_MASK 0x7 -#define MCCH_PrefDramTrainMode (1<<28) -#define MCCH_FlushWrOnStpGnt (1<<29) -#define MCCH_FlushWr (1<<30) -#define MCCH_MctScrubEn (1<<31) +#define MCCH_PrefDramTrainMode (1 << 28) +#define MCCH_FlushWrOnStpGnt (1 << 29) +#define MCCH_FlushWr (1 << 30) +#define MCCH_MctScrubEn (1 << 31) /* Function 3 */ #define MCA_NB_CONTROL 0x40 -#define MNCT_CorrEccEn (1<<0) -#define MNCT_UnCorrEccEn (1<<1) -#define MNCT_CrcErr0En (1<<2) /* Link 0 */ -#define MNCT_CrcErr1En (1<<3) -#define MNCT_CrcErr2En (1<<4) -#define MBCT_SyncPkt0En (1<<5) /* Link 0 */ -#define MBCT_SyncPkt1En (1<<6) -#define MBCT_SyncPkt2En (1<<7) -#define MBCT_MstrAbrtEn (1<<8) -#define MBCT_TgtAbrtEn (1<<9) -#define MBCT_GartTblEkEn (1<<10) -#define MBCT_AtomicRMWEn (1<<11) -#define MBCT_WdogTmrRptEn (1<<12) -#define MBCT_DevErrEn (1<<13) -#define MBCT_L3ArrayCorEn (1<<14) -#define MBCT_L3ArrayUncEn (1<<15) -#define MBCT_HtProtEn (1<<16) -#define MBCT_HtDataEn (1<<17) -#define MBCT_DramParEn (1<<18) -#define MBCT_RtryHt0En (1<<19) /* Link 0 */ -#define MBCT_RtryHt1En (1<<20) -#define MBCT_RtryHt2En (1<<21) -#define MBCT_RtryHt3En (1<<22) -#define MBCT_CrcErr3En (1<<23) /* Link 3*/ -#define MBCT_SyncPkt3En (1<<24) /* Link 4 */ -#define MBCT_McaUsPwDatErrEn (1<<25) -#define MBCT_NbArrayParEn (1<<26) -#define MBCT_TblWlkDatErrEn (1<<27) -#define MBCT_FbDimmCorErrEn (1<<28) -#define MBCT_FbDimmUnCorErrEn (1<<29) +#define MNCT_CorrEccEn (1 << 0) +#define MNCT_UnCorrEccEn (1 << 1) +#define MNCT_CrcErr0En (1 << 2) /* Link 0 */ +#define MNCT_CrcErr1En (1 << 3) +#define MNCT_CrcErr2En (1 << 4) +#define MBCT_SyncPkt0En (1 << 5) /* Link 0 */ +#define MBCT_SyncPkt1En (1 << 6) +#define MBCT_SyncPkt2En (1 << 7) +#define MBCT_MstrAbrtEn (1 << 8) +#define MBCT_TgtAbrtEn (1 << 9) +#define MBCT_GartTblEkEn (1 << 10) +#define MBCT_AtomicRMWEn (1 << 11) +#define MBCT_WdogTmrRptEn (1 << 12) +#define MBCT_DevErrEn (1 << 13) +#define MBCT_L3ArrayCorEn (1 << 14) +#define MBCT_L3ArrayUncEn (1 << 15) +#define MBCT_HtProtEn (1 << 16) +#define MBCT_HtDataEn (1 << 17) +#define MBCT_DramParEn (1 << 18) +#define MBCT_RtryHt0En (1 << 19) /* Link 0 */ +#define MBCT_RtryHt1En (1 << 20) +#define MBCT_RtryHt2En (1 << 21) +#define MBCT_RtryHt3En (1 << 22) +#define MBCT_CrcErr3En (1 << 23) /* Link 3*/ +#define MBCT_SyncPkt3En (1 << 24) /* Link 4 */ +#define MBCT_McaUsPwDatErrEn (1 << 25) +#define MBCT_NbArrayParEn (1 << 26) +#define MBCT_TblWlkDatErrEn (1 << 27) +#define MBCT_FbDimmCorErrEn (1 << 28) +#define MBCT_FbDimmUnCorErrEn (1 << 29) #define MCA_NB_CONFIG 0x44 -#define MNC_CpuRdDatErrEn (1<<1) -#define MNC_SyncOnUcEccEn (1<<2) -#define MNC_SynvPktGenDis (1<<3) -#define MNC_SyncPktPropDis (1<<4) -#define MNC_IoMstAbortDis (1<<5) -#define MNC_CpuErrDis (1<<6) -#define MNC_IoErrDis (1<<7) -#define MNC_WdogTmrDis (1<<8) +#define MNC_CpuRdDatErrEn (1 << 1) +#define MNC_SyncOnUcEccEn (1 << 2) +#define MNC_SynvPktGenDis (1 << 3) +#define MNC_SyncPktPropDis (1 << 4) +#define MNC_IoMstAbortDis (1 << 5) +#define MNC_CpuErrDis (1 << 6) +#define MNC_IoErrDis (1 << 7) +#define MNC_WdogTmrDis (1 << 8) #define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ #define MNC_WdogTmrCntSel_2_0_MASK 0x3 #define MNC_WdogTmrBaseSel_SHIFT 12 #define MNC_WdogTmrBaseSel_MASK 0x3 #define MNC_LdtLinkSel_SHIFT 14 #define MNC_LdtLinkSel_MASK 0x3 -#define MNC_GenCrcErrByte0 (1<<16) -#define MNC_GenCrcErrByte1 (1<<17) +#define MNC_GenCrcErrByte0 (1 << 16) +#define MNC_GenCrcErrByte1 (1 << 17) #define MNC_SubLinkSel_SHIFT 18 #define MNC_SubLinkSel_MASK 0x3 -#define MNC_SyncOnWdogEn (1<<20) -#define MNC_SyncOnAnyErrEn (1<<21) -#define MNC_DramEccEn (1<<22) -#define MNC_ChipKillEccEn (1<<23) -#define MNC_IoRdDatErrEn (1<<24) -#define MNC_DisPciCfgCpuErrRsp (1<<25) -#define MNC_CorrMcaExcEn (1<<26) -#define MNC_NbMcaToMstCpuEn (1<<27) -#define MNC_DisTgtAbtCpuErrRsp (1<<28) -#define MNC_DisMstAbtCpuErrRsp (1<<29) -#define MNC_SyncOnDramAdrParErrEn (1<<30) -#define MNC_NbMcaLogEn (1<<31) +#define MNC_SyncOnWdogEn (1 << 20) +#define MNC_SyncOnAnyErrEn (1 << 21) +#define MNC_DramEccEn (1 << 22) +#define MNC_ChipKillEccEn (1 << 23) +#define MNC_IoRdDatErrEn (1 << 24) +#define MNC_DisPciCfgCpuErrRsp (1 << 25) +#define MNC_CorrMcaExcEn (1 << 26) +#define MNC_NbMcaToMstCpuEn (1 << 27) +#define MNC_DisTgtAbtCpuErrRsp (1 << 28) +#define MNC_DisMstAbtCpuErrRsp (1 << 29) +#define MNC_SyncOnDramAdrParErrEn (1 << 30) +#define MNC_NbMcaLogEn (1 << 31) #define MCA_NB_STATUS_LOW 0x48 #define MNSL_ErrorCode_SHIFT 0 @@ -734,22 +734,22 @@ #define MNSH_ErrCPU_MASK 0xf #define MNSH_LDTLink_SHIFT 4 #define MNSH_LDTLink_MASK 0xf -#define MNSH_ErrScrub (1<<8) -#define MNSH_SubLink (1<<9) +#define MNSH_ErrScrub (1 << 8) +#define MNSH_SubLink (1 << 9) #define MNSH_McaStatusSubCache_SHIFT 10 #define MNSH_McaStatusSubCache_MASK 0x3 -#define MNSH_Deffered (1<<12) -#define MNSH_UnCorrECC (1<<13) -#define MNSH_CorrECC (1<<14) +#define MNSH_Deffered (1 << 12) +#define MNSH_UnCorrECC (1 << 13) +#define MNSH_CorrECC (1 << 14) #define MNSH_Syndrome_7_0_SHIFT 15 #define MNSH_Syndrome_7_0_MASK 0xff -#define MNSH_PCC (1<<25) -#define MNSH_ErrAddrVal (1<<26) -#define MNSH_ErrMiscVal (1<<27) -#define MNSH_ErrEn (1<<28) -#define MNSH_ErrUnCorr (1<<29) -#define MNSH_ErrOver (1<<30) -#define MNSH_ErrValid (1<<31) +#define MNSH_PCC (1 << 25) +#define MNSH_ErrAddrVal (1 << 26) +#define MNSH_ErrMiscVal (1 << 27) +#define MNSH_ErrEn (1 << 28) +#define MNSH_ErrUnCorr (1 << 29) +#define MNSH_ErrOver (1 << 30) +#define MNSH_ErrValid (1 << 31) #define MCA_NB_ADDR_LOW 0x50 #define MNAL_ErrAddr_31_1_SHIFT 1 @@ -793,7 +793,7 @@ #define DSRC_L3Scrub_MASK 0x1f #define DRAM_SCRUB_ADDR_LOW 0x5C -#define DSAL_ScrubReDirEn (1<<0) +#define DSAL_ScrubReDirEn (1 << 0) #define DSAL_ScrubAddrLo_SHIFT 6 #define DSAL_ScrubAddrLo_MASK 0x3ffffff @@ -863,8 +863,8 @@ #define NBCAP_DdrMaxRate_8_0G 2 #define NBCAP_DdrMaxRate_9_6G 1 #define NBCAP_Mem_ctrl_cap (1 << 8) -#define MBCAP_SVMCap (1<<9) -#define NBCAP_HtcCap (1<<10) +#define MBCAP_SVMCap (1 << 9) +#define NBCAP_HtcCap (1 << 10) #define NBCAP_CmpCap_SHIFT 12 #define NBCAP_CmpCap_MASK 3 #define NBCAP_MpCap_SHIFT 16 @@ -876,8 +876,8 @@ #define NBCAP_MpCap_32N 0 #define NBCAP_UnGangEn_SHIFT 20 #define NBCAP_UnGangEn_MASK 0xf -#define NBCAP_L3Cap (1<<25) -#define NBCAP_HtAcCap (1<<26) +#define NBCAP_L3Cap (1 << 25) +#define NBCAP_HtAcCap (1 << 26) /* 04/04/2006 18:00 */ diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index c3b02d7..bfb7940 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -25,7 +25,7 @@ #if CONFIG_EXT_RT_TBL_SUPPORT u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); - dword |= (1<<27) | (1<<25); + dword |= (1 << 27) | (1 << 25); /* CHtExtNodeCfgEn: coherent link extended node configuration enable, Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0] ---- 32 nodes now only diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index 08698dc..923600c 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -58,7 +58,7 @@ int i,j; u32 dword; - dword = sysconf.sblk<<8; + dword = sysconf.sblk << 8; dword |= 1; sysconf.pci1234[0] = dword; // sblink sysconf.hcid[0] = 0; diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 916111c..e18a361 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -32,14 +32,14 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -163,9 +163,9 @@ index = (reg-0xc0)>>3; val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid val = 3 | ((linkn & 0x7)<<4); // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit if (sysconf.io_addr_num < (index+1)) sysconf.io_addr_num = index+1; @@ -197,11 +197,11 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -212,7 +212,7 @@ u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 7cd9bff..def466a 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -89,7 +89,7 @@ resource->flags |= IORESOURCE_STORED; /* Find the size of the GART aperture */ - gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); + gart_acr = (0 << 6)|(0 << 5)|(0 << 4)|((resource->gran - 25) << 1)|(0 << 0); /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; @@ -194,7 +194,7 @@ * This is needed for PC backwards compatibility. */ dword = pci_read_config32(dev, 0x44); - dword |= (1<<6) | (1<<25); + dword |= (1 << 6) | (1 << 25); pci_write_config32(dev, 0x44, dword); boost_limit = 0xf; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dccd9c6..4be52f7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -138,7 +138,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); @@ -426,7 +426,7 @@ if (!reg) { //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -461,7 +461,7 @@ // but we need one index to differ them. so same node and // same link can have multi range u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63 } resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -852,7 +852,7 @@ hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } @@ -1448,7 +1448,7 @@ nb_cfg_54 = 0; ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); if (ApicIdCoreIdSize) { - siblings = (1<<ApicIdCoreIdSize)-1; + siblings = (1 << ApicIdCoreIdSize)-1; } else { siblings = 3; //quad core } diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c index 6c6d717..250ded4 100644 --- a/src/northbridge/amd/amdfam10/pci.c +++ b/src/northbridge/amd/amdfam10/pci.c @@ -44,11 +44,11 @@ u32 dword; - index &= ~(1<<30); + index &= ~(1 << 30); pci_write_config32(dev, index_reg, index); do { dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + } while (!(dword & (1 << 31))); dword = pci_read_config32(dev, index_reg+0x4); return dword; } @@ -61,11 +61,11 @@ u32 dword; pci_write_config32(dev, index_reg + 0x4, data); - index |= (1<<30); + index |= (1 << 30); pci_write_config32(dev, index_reg, index); do { dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + } while (!(dword & (1 << 31))); } #endif diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c index dce2053..3044095 100644 --- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c +++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c @@ -21,7 +21,7 @@ { u32 dword; dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); - dword &= ~(1<<bit); + dword &= ~(1 << bit); dword |= ((val & 1) <<bit); pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword); } @@ -31,7 +31,7 @@ { u32 dword; dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL); - dword &= (1<<bit); + dword &= (1 << bit); return dword; } diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 85cbbc4..d2c85ae 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -38,7 +38,7 @@ AmdPCIRead(loc, pValue); *pValue = *pValue >> lowbit; /* Shift */ - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ + /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */ if ((highbit-lowbit) != 31) *pValue &= (((u32)1 << (highbit-lowbit+1))-1); } @@ -50,7 +50,7 @@ ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ + /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */ if ((highbit-lowbit) != 31) mask = (((u32)1 << (highbit-lowbit+1))-1); else diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 6a9d898..fbb2e67 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -846,7 +846,7 @@ for (k = 0; k < MAX_NODES; k++) { - if (AbstractBcTargetNodes & ((u32)1<<k)) + if (AbstractBcTargetNodes & ((u32)1 << k)) { BcTargetLinks |= (u32)1 << convertNodeToLink(i, pDat->ReversePerm[k], pDat); } diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 5f656f5..281566c 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -178,7 +178,7 @@ ASSERT((hiBit < 32) && (loBit < 32) && (hiBit >= loBit) && ((reg & 0x3) == 0)); ASSERT((hiBit < 8) || (loBit > 9)); - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ + /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */ if ((hiBit-loBit) != 31) mask = (((u32)1 << (hiBit-loBit+1))-1); else diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e335a98..3cd8174 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -11,9 +11,9 @@ #include "pre_f.h" #endif -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) #define NODE_HT(x) PCI_DEV(0,24+x,0) #define NODE_MP(x) PCI_DEV(0,24+x,1) diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 10ca6ee..e688d4f 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -178,7 +178,7 @@ printk(BIOS_SPEW, "Enabling routing table for node %d", node); val = pci_read_config32(NODE_HT(node), 0x6c); - val &= ~((1<<1)|(1<<0)); + val &= ~((1 << 1)|(1 << 0)); pci_write_config32(NODE_HT(node), 0x6c, val); printk(BIOS_SPEW, " done.\n"); @@ -187,7 +187,7 @@ #if CONFIG_MAX_PHYSICAL_CPUS > 1 static void fill_row(u8 node, u8 row, u32 value) { - pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); + pci_write_config32(NODE_HT(node), 0x40+(row << 2), value); } static u8 link_to_register(int ldt) @@ -211,7 +211,7 @@ static u32 get_row(u8 node, u8 row) { - return pci_read_config32(NODE_HT(node), 0x40+(row<<2)); + return pci_read_config32(NODE_HT(node), 0x40+(row << 2)); } static int link_connection(u8 src, u8 dest) @@ -411,7 +411,7 @@ //(6,5) (7,4) should be here #endif ) { - val |= (1<<16); + val |= (1 << 16); } else { /*for CROSS_BAR_47_56 47, 56, should be here too and for 47, 56, 57, 75, 46, 64 we need to substract another link to @@ -559,11 +559,11 @@ } #endif val &= 0xff; - val |= (val_s<<8); + val |= (val_s << 8); } if (diff) { /* cross rung?*/ - val |= (1<<16); + val |= (1 << 16); } else { val_s = get_row(temp, source); @@ -1615,15 +1615,15 @@ */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { - cmd &= ~(3<<0); - cmd |= (2<<0); + cmd &= ~(3 << 0); + cmd |= (2 << 0); pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { - cmd &= ~(3<<4); - cmd |= (0<<4); + cmd &= ~(3 << 4); + cmd |= (0 << 4); pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index f3f9c42..cbed691 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -65,24 +65,24 @@ #define DC_RdPadRcvFiloDly_2_5_CLK 4 #define DC_RdPadRcvFiloDly_3_CLK 5 #define DC_RdPadRcvFiloDly_3_5_CLK 6 -#define DC_AltVidC3MemClkTriEn (1<<16) +#define DC_AltVidC3MemClkTriEn (1 << 16) #define DC_DllTempAdjTime_SHIFT 17 #define DC_DllTempAdjTime_MASK 1 #define DC_DllTempAdjTime_5_MS 0 #define DC_DllTempAdjTime_1_MS 1 -#define DC_DqsRcvEnTrain (1<<18) +#define DC_DqsRcvEnTrain (1 << 18) #define DRAM_INIT 0x7c #define DI_MrsAddress_SHIFT 0 #define DI_MrsAddress_MASK 0xffff #define DI_MrsBank_SHIFT 16 #define DI_MrsBank_MASK 7 -#define DI_SendRchgAll (1<<24) -#define DI_SendAutoRefresh (1<<25) -#define DI_SendMrsCmd (1<<26) -#define DI_DeassertMemRstX (1<<27) -#define DI_AssertCke (1<<28) -#define DI_EnDramInit (1<<31) +#define DI_SendRchgAll (1 << 24) +#define DI_SendAutoRefresh (1 << 25) +#define DI_SendMrsCmd (1 << 26) +#define DI_DeassertMemRstX (1 << 27) +#define DI_AssertCke (1 << 28) +#define DI_EnDramInit (1 << 31) #define DRAM_TIMING_LOW 0x88 #define DTL_TCL_SHIFT 0 @@ -178,23 +178,23 @@ #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */ #define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) -#define DCL_ExitSelfRef (1<<1) +#define DCL_InitDram (1 << 0) +#define DCL_ExitSelfRef (1 << 1) #define DCL_DramTerm_SHIFT 4 #define DCL_DramTerm_MASK 3 #define DCL_DramTerm_No 0 #define DCL_DramTerm_75_OH 1 #define DCL_DramTerm_150_OH 2 #define DCL_DramTerm_50_OH 3 -#define DCL_DrvWeak (1<<7) -#define DCL_ParEn (1<<8) -#define DCL_SelfRefRateEn (1<<9) -#define DCL_BurstLength32 (1<<10) -#define DCL_Width128 (1<<11) +#define DCL_DrvWeak (1 << 7) +#define DCL_ParEn (1 << 8) +#define DCL_SelfRefRateEn (1 << 9) +#define DCL_BurstLength32 (1 << 10) +#define DCL_Width128 (1 << 11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) -#define DCL_DimmEccEn (1<<19) +#define DCL_UnBuffDimm (1 << 16) +#define DCL_DimmEccEn (1 << 19) #define DRAM_CONFIG_HIGH 0x94 #define DCH_MemClkFreq_SHIFT 0 @@ -203,23 +203,23 @@ #define DCH_MemClkFreq_266MHz 1 #define DCH_MemClkFreq_333MHz 2 #define DCH_MemClkFreq_400MHz 3 -#define DCH_MemClkFreqVal (1<<3) +#define DCH_MemClkFreqVal (1 << 3) #define DCH_MaxAsyncLat_SHIFT 4 #define DCH_MaxAsyncLat_MASK 0xf #define DCH_MaxAsyncLat_BASE 0 #define DCH_MaxAsyncLat_MIN 0 #define DCH_MaxAsyncLat_MAX 15 -#define DCH_RDqsEn (1<<12) -#define DCH_DisDramInterface (1<<14) -#define DCH_PowerDownEn (1<<15) +#define DCH_RDqsEn (1 << 12) +#define DCH_DisDramInterface (1 << 14) +#define DCH_PowerDownEn (1 << 15) #define DCH_PowerDownMode_SHIFT 16 #define DCH_PowerDownMode_MASK 1 #define DCH_PowerDownMode_Channel_CKE 0 #define DCH_PowerDownMode_ChipSelect_CKE 1 -#define DCH_FourRankSODimm (1<<17) -#define DCH_FourRankRDimm (1<<18) -#define DCH_SlowAccessMode (1<<19) -#define DCH_BankSwizzleMode (1<<22) +#define DCH_FourRankSODimm (1 << 17) +#define DCH_FourRankRDimm (1 << 18) +#define DCH_SlowAccessMode (1 << 19) +#define DCH_BankSwizzleMode (1 << 22) #define DCH_DcqBypassMax_SHIFT 24 #define DCH_DcqBypassMax_MASK 0xf #define DCH_DcqBypassMax_BASE 0 @@ -236,8 +236,8 @@ #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 #define DCAO_DctOffset_MASK 0x3fffffff -#define DCAO_DctAccessWrite (1<<30) -#define DCAO_DctAccessDone (1<<31) +#define DCAO_DctAccessWrite (1 << 30) +#define DCAO_DctAccessDone (1 << 31) #define DRAM_CTRL_ADDI_DATA_PORT 0x9c @@ -313,19 +313,19 @@ #define DATC_CkeFineDelay_BASE 0 #define DATC_CkeFineDelay_MIN 0 #define DATC_CkeFineDelay_MAX 31 -#define DATC_CkeSetup (1<<5) +#define DATC_CkeSetup (1 << 5) #define DATC_CsOdtFineDelay_SHIFT 8 #define DATC_CsOdtFineDelay_MASK 0x1f #define DATC_CsOdtFineDelay_BASE 0 #define DATC_CsOdtFineDelay_MIN 0 #define DATC_CsOdtFineDelay_MAX 31 -#define DATC_CsOdtSetup (1<<13) +#define DATC_CsOdtSetup (1 << 13) #define DATC_AddrCmdFineDelay_SHIFT 16 #define DATC_AddrCmdFineDelay_MASK 0x1f #define DATC_AddrCmdFineDelay_BASE 0 #define DATC_AddrCmdFineDelay_MIN 0 #define DATC_AddrCmdFineDelay_MAX 31 -#define DATC_AddrCmdSetup (1<<21) +#define DATC_AddrCmdSetup (1 << 21) #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 #define DRDTCL_RdDqsTimeByte0_SHIFT 0 @@ -365,16 +365,16 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 */ #define DRAM_CTRL_MISC 0xa0 -#define DCM_MemClrStatus (1<<0) -#define DCM_DisableJitter (1<<1) +#define DCM_MemClrStatus (1 << 0) +#define DCM_DisableJitter (1 << 1) #define DCM_RdWrQByp_SHIFT 2 #define DCM_RdWrQByp_MASK 3 #define DCM_RdWrQByp_2 0 #define DCM_RdWrQByp_4 1 #define DCM_RdWrQByp_8 2 #define DCM_RdWrQByp_16 3 -#define DCM_Mode64BitMux (1<<4) -#define DCM_DCC_EN (1<<5) +#define DCM_Mode64BitMux (1 << 4) +#define DCM_DCC_EN (1 << 5) #define DCM_ILD_lmt_SHIFT 6 #define DCM_ILD_lmt_MASK 7 #define DCM_ILD_lmt_0 0 @@ -385,7 +385,7 @@ #define DCM_ILD_lmt_64 5 #define DCM_ILD_lmt_128 6 #define DCM_ILD_lmt_256 7 -#define DCM_DramEnabled (1<<9) +#define DCM_DramEnabled (1 << 9) #define DCM_MemClkDis_SHIFT 24 /* Channel B */ #define DCM_MemClkDis3 (1 << 26) #define DCM_MemClkDis2 (1 << 27) @@ -446,7 +446,7 @@ #define NBCAP_MEMCLK_333MHZ 1 #define NBCAP_MEMCLK_NOLIMIT 0 #define NBCAP_MEMCTRL (1 << 8) -#define NBCAP_HtcCap (1<<10) +#define NBCAP_HtcCap (1 << 10) #define NBCAP_CmpCap_SHIFT 12 #define NBCAP_CmpCap_MASK 3 @@ -541,15 +541,15 @@ /* Skip everything if I don't have any memory on this controller */ if (sysinfo->mem_trained[i]== 0x00) continue; - mask |= (1<<i); + mask |= (1 << i); } i = 1; while (1) { - if (mask & (1<<i)) { + if (mask & (1 << i)) { if ((sysinfo->mem_trained[i])!=0x80) { - mask &= ~(1<<i); + mask &= ~(1 << i); } } diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index 230333a..ac2f2ff 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -31,12 +31,12 @@ { uint32_t dword; - index &= ~(1<<30); + index &= ~(1 << 30); pci_write_config32(dev, index_reg, index); do { dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + } while (!(dword & (1 << 31))); dword = pci_read_config32(dev, index_reg+0x4); @@ -50,11 +50,11 @@ pci_write_config32(dev, index_reg + 0x4, data); - index |= (1<<30); + index |= (1 << 30); pci_write_config32(dev, index_reg, index); do { dword = pci_read_config32(dev, index_reg); - } while (!(dword & (1<<31))); + } while (!(dword & (1 << 31))); } #endif diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d65af96..ac513aa 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -624,7 +624,7 @@ busn = (reg & 0xff0000)>>16; dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos); - dword &= ~(0xffff<<8); + dword &= ~(0xffff << 8); dword |= (reg & 0xffff0000)>>8; pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword); @@ -677,16 +677,16 @@ sysinfo->sbbusn = 0; sysinfo->nodes = nodes; #endif - tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); + tempreg = 3 | (0 << 4) | (((reg>>8) & 3)<<8) | (0 << 16)| (0x3f << 24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg); next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ #if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ - tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit + tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3 << 12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg); - tempreg = 3 | (3<<4) | (0<<12); //base + tempreg = 3 | (3 << 4) | (0 << 12); //base pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg); next_io_base = 0x3+0x1; #endif @@ -712,7 +712,7 @@ reg = pci_read_config32(dev, regpos); if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/ print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); - tempreg = 3 | (nodeid <<4) | (linkn<<8); + tempreg = 3 | (nodeid <<4) | (linkn << 8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); @@ -724,15 +724,15 @@ /*update to 0xe0...*/ if ((reg & 0xf) == 3) continue; /*SbLink so don't touch it */ print_linkn_in("\tbusn=", next_busn); - tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24); + tempreg |= (next_busn << 16)|((next_busn+0x3f)<<24); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); next_busn+=0x3f+1; #if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ - tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit + tempreg = nodeid | (linkn << 4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); - tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | (next_io_base << 12); //base :ISA and VGA ? pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); next_io_base += 0x3+0x1; #endif diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 3cbeb04..9c43156 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -74,7 +74,7 @@ resource->flags |= IORESOURCE_STORED; /* Find the size of the GART aperture */ - gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0); + gart_acr = (0 << 6)|(0 << 5)|(0 << 4)|((resource->gran - 25) << 1)|(0 << 0); /* Get the base address */ gart_base = ((resource->base) >> 25) & 0x00007fff; @@ -119,7 +119,7 @@ * This is needed for PC backwards compatibility. */ cmd = pci_read_config32(dev, 0x44); - cmd |= (1<<6) | (1<<25); + cmd |= (1 << 6) | (1 << 25); pci_write_config32(dev, 0x44, cmd); #if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { @@ -128,11 +128,11 @@ * Disable CPU low power states C2, C1 and throttling */ cmd = pci_read_config32(dev, 0x80); - cmd &= ~(1<<0); + cmd &= ~(1 << 0); pci_write_config32(dev, 0x80, cmd); cmd = pci_read_config32(dev, 0x84); - cmd &= ~(1<<24); - cmd &= ~(1<<8); + cmd &= ~(1 << 24); + cmd &= ~(1 << 8); pci_write_config32(dev, 0x84, cmd); /* Errata 66 @@ -140,15 +140,15 @@ */ cmd = pci_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { - cmd &= ~(3<<0); - cmd |= (2<<0); + cmd &= ~(3 << 0); + cmd |= (2 << 0); pci_write_config32(dev, 0x70, cmd); needs_reset = 1; } cmd = pci_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { - cmd &= ~(3<<4); - cmd |= (0<<4); + cmd &= ~(3 << 4); + cmd |= (0 << 4); pci_write_config32(dev, 0x7c, cmd); needs_reset = 1; } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c957af0..d7386c9 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -674,13 +674,13 @@ u32 base; u32 hole; base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } @@ -695,7 +695,7 @@ u32 base, limit; unsigned base_k, limit_k; base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } @@ -735,7 +735,7 @@ for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } limit = f1_read_config32(0x44 + (i << 3)); @@ -772,7 +772,7 @@ for (i = 7; i > node_id; i--) { base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } limit = f1_read_config32(0x44 + (i << 3)); @@ -789,7 +789,7 @@ //so need to change base reg instead, new basek will be 4*1024*1024 base &= 0x0000ffff; base |= (4*1024*1024)<<2; - f1_write_config32(0x40 + (node_id<<3), base); + f1_write_config32(0x40 + (node_id << 3), base); } else if (dev) { @@ -910,7 +910,7 @@ u32 base; u32 basek; base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } @@ -936,7 +936,7 @@ u32 basek, limitk, sizek; base = f1_read_config32(0x40 + (i << 3)); limit = f1_read_config32(0x44 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } basek = (base & 0xffff0000) >> 2; diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index abc51b1..479ceb4 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -125,26 +125,26 @@ #define DTH_TWCL_MAX 2 #define DRAM_CONFIG_LOW 0x90 -#define DCL_DLL_Disable (1<<0) -#define DCL_D_DRV (1<<1) -#define DCL_QFC_EN (1<<2) -#define DCL_DisDqsHys (1<<3) -#define DCL_Burst2Opt (1<<5) -#define DCL_DramInit (1<<8) -#define DCL_DualDIMMen (1<<9) -#define DCL_DramEnable (1<<10) -#define DCL_MemClrStatus (1<<11) -#define DCL_ESR (1<<12) -#define DCL_SRS (1<<13) -#define DCL_128BitEn (1<<16) -#define DCL_DimmEccEn (1<<17) -#define DCL_UnBuffDimm (1<<18) -#define DCL_32ByteEn (1<<19) +#define DCL_DLL_Disable (1 << 0) +#define DCL_D_DRV (1 << 1) +#define DCL_QFC_EN (1 << 2) +#define DCL_DisDqsHys (1 << 3) +#define DCL_Burst2Opt (1 << 5) +#define DCL_DramInit (1 << 8) +#define DCL_DualDIMMen (1 << 9) +#define DCL_DramEnable (1 << 10) +#define DCL_MemClrStatus (1 << 11) +#define DCL_ESR (1 << 12) +#define DCL_SRS (1 << 13) +#define DCL_128BitEn (1 << 16) +#define DCL_DimmEccEn (1 << 17) +#define DCL_UnBuffDimm (1 << 18) +#define DCL_32ByteEn (1 << 19) #define DCL_x4DIMM_SHIFT 20 -#define DCL_DisInRcvrs (1<<24) +#define DCL_DisInRcvrs (1 << 24) #define DCL_BypMax_SHIFT 25 -#define DCL_En2T (1<<28) -#define DCL_UpperCSMap (1<<29) +#define DCL_En2T (1 << 28) +#define DCL_UpperCSMap (1 << 29) #define DRAM_CONFIG_HIGH 0x94 #define DCH_ASYNC_LAT_SHIFT 0 @@ -154,9 +154,9 @@ #define DCH_ASYNC_LAT_MAX 15 #define DCH_RDPREAMBLE_SHIFT 8 #define DCH_RDPREAMBLE_MASK 0xf -#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ -#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ -#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_RDPREAMBLE_BASE ((2 << 1)+0) /* 2.0 ns */ +#define DCH_RDPREAMBLE_MIN ((2 << 1)+0) /* 2.0 ns */ +#define DCH_RDPREAMBLE_MAX ((9 << 1)+1) /* 9.5 ns */ #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 43229ea..832a04f 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -829,7 +829,7 @@ limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; - base |= (0 << 8) | (1<<1) | (1<<0); + base |= (0 << 8) | (1 << 1) | (1 << 0); limit_reg = 0x44 + index; base_reg = 0x40 + index; @@ -1320,7 +1320,7 @@ [NBCAP_MEMCLK_133MHZ] = { .name = "133MHz", .cycle_time = 0x75, - .divisor = (7<<1)+1, + .divisor = (7 << 1)+1, .tRC = 0x41, .tRFC = 0x4B, .dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT, @@ -1334,7 +1334,7 @@ [NBCAP_MEMCLK_166MHZ] = { .name = "166MHz", .cycle_time = 0x60, - .divisor = (6<<1), + .divisor = (6 << 1), .tRC = 0x3C, .tRFC = 0x48, .dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT, @@ -1348,7 +1348,7 @@ [NBCAP_MEMCLK_200MHZ] = { .name = "200MHz", .cycle_time = 0x50, - .divisor = (5<<1), + .divisor = (5 << 1), .tRC = 0x37, .tRFC = 0x46, .dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT, @@ -2230,7 +2230,7 @@ for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); @@ -2252,7 +2252,7 @@ base &= 0x0000ffff; base |= (4*1024*1024)<<2; for (j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + pci_write_config32(ctrl[j].f1, 0x40 + (i << 3), base); } } else { @@ -2287,7 +2287,7 @@ uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } base_k = (base & 0xffff0000) >> 2; @@ -2308,7 +2308,7 @@ uint32_t base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index a979896..c508817 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -253,7 +253,7 @@ * 1 = DQS receiver enable training mode * [31:19] reserved */ - PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0), + PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6 << 4)|(6 << 0), /* DRAM Initialization Register * F2:0x7C @@ -1005,7 +1005,7 @@ limit |= (0 << 8) | (node_id << 0); base = (base_k << 2); base &= 0xffff0000; - base |= (0 << 8) | (1<<1) | (1<<0); + base |= (0 << 8) | (1 << 1) | (1 << 0); limit_reg = 0x44 + index; base_reg = 0x40 + index; @@ -1329,7 +1329,7 @@ value &= 0x3f; if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) { //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)? - registered |= (1<<i); + registered |= (1 << i); } } @@ -2236,11 +2236,11 @@ } if (meminfo->sz[i].rank == 1) { - mask_single_rank |= 1<<i; + mask_single_rank |= 1 << i; } if (meminfo->sz[i].col == 10) { - mask_page_1k |= 1<<i; + mask_page_1k |= 1 << i; } @@ -2251,14 +2251,14 @@ #endif if (value == 4) { - mask_x4 |= (1<<i); + mask_x4 |= (1 << i); #if CONFIG_QRANK_DIMM_SUPPORT if (rank == 4) { mask_x4 |= 1<<(i+2); } #endif } else if (value == 16) { - mask_x16 |= (1<<i); + mask_x16 |= (1 << i); #if CONFIG_QRANK_DIMM_SUPPORT if (rank == 4) { mask_x16 |= 1<<(i+2); @@ -2283,7 +2283,7 @@ { uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT); + dcl &= ~(DCL_X4Dimm_MASK << DCL_X4Dimm_SHIFT); dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT); pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } @@ -2325,7 +2325,7 @@ #endif dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT); + dcl &= ~(DCL_DramTerm_MASK << DCL_DramTerm_SHIFT); dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT); pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } @@ -2482,7 +2482,7 @@ dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); - dch |= (1<<20); + dch |= (1 << 20); pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } @@ -2883,7 +2883,7 @@ for (ii = controllers - 1; ii > i; ii--) { base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); @@ -2908,7 +2908,7 @@ base &= 0x0000ffff; base |= (4*1024*1024)<<2; for (j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + pci_write_config32(ctrl[j].f1, 0x40 + (i << 3), base); } } else { hoist = /* hole start address */ @@ -2940,7 +2940,7 @@ uint32_t base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) { continue; } base_k = (base & 0xffff0000) >> 2; @@ -3129,11 +3129,11 @@ msr_t msr; //[1M, TOM) msr = rdmsr(TOP_MEM); - sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2; + sysinfo->tom_k = ((msr.hi << 24) | (msr.lo>>8))>>2; //[4G, TOM2) msr = rdmsr(TOP_MEM2); - sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2; + sysinfo->tom2_k = ((msr.hi << 24)| (msr.lo>>8))>>2; } for (i = 0; i < controllers; i++) { diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index c470b25..dc91598 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -122,7 +122,7 @@ { unsigned long cr4; cr4 = read_cr4(); - cr4 |= (1<<9); + cr4 |= (1 << 9); write_cr4(cr4); } @@ -130,7 +130,7 @@ { unsigned long cr4; cr4 = read_cr4(); - cr4 &= ~(1<<9); + cr4 &= ~(1 << 9); write_cr4(cr4); } @@ -139,7 +139,7 @@ msr_t msr; msr = rdmsr(0xc0010015); - msr.lo |= (1<<17); + msr.lo |= (1 << 17); wrmsr(0xc0010015, msr); @@ -149,7 +149,7 @@ msr_t msr; msr = rdmsr(0xc0010015); - msr.lo &= ~(1<<17); + msr.lo &= ~(1 << 17); wrmsr(0xc0010015, msr); @@ -1713,7 +1713,7 @@ if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); - msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB + msr.lo |= (1 << 21) | (1 << 22); //MtrrTom2En and Tom2ForceMemTypeWB wrmsr(SYSCFG_MSR, msr); } @@ -1744,7 +1744,7 @@ if (tom2_k) { //enable tom2 and type msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB + msr.lo &= ~((1 << 21) | (1 << 22)); //MtrrTom2En and Tom2ForceMemTypeWB wrmsr(SYSCFG_MSR, msr); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 8bee434..4c1c96f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -475,7 +475,7 @@ for (Channel = 0; Channel < 2; Channel++) { reg = 0x78 + Channel * 0x100; val = Get_NB32(dev, reg); - val &= ~(0x3ff<<22); + val &= ~(0x3ff << 22); val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22); val &= ~(1 << DqsRcvEnTrain); Set_NB32(dev, reg, val); /* program MaxRdLatency to correspond with current delay*/ @@ -830,7 +830,7 @@ } if (stopDCTflag) { u32 reg_off = dct * 0x100; - val = 1<<DisDramInterface; + val = 1 << DisDramInterface; Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val); /*To maximize power savings when DisDramInterface = 1b, all of the MemClkDis bits should also be set.*/ @@ -1048,7 +1048,7 @@ val = mctRead_SPD(smbaddr, SPD_TRC); if ((val == 0) || (val == 0xFF)) { - pDCTstat->ErrStatus |= 1<<SB_NoTrcTrfc; + pDCTstat->ErrStatus |= 1 << SB_NoTrcTrfc; pDCTstat->ErrCode = SC_VarianceErr; val = Get_DefTrc_k_D(pDCTstat->Speed); } else { @@ -1532,7 +1532,7 @@ DramControl = Get_NB32 (dev, 0x78 + reg_off); /* Dram Control*/ if (mctGet_NVbits(NV_CLKHZAltVidC3)) - DramControl |= 1<<16; + DramControl |= 1 << 16; // FIXME: Add support(skip) for Ax and Cx versions DramControl |= 5; /* RdPtrInit */ @@ -1952,7 +1952,7 @@ if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) { word = pDCTstat->CSPresent; val = bsf(word); - word &= ~(1<<val); + word &= ~(1 << val); if (word) /* Make sure at least two chip-selects are available */ _DSpareEn = 1; @@ -2054,13 +2054,13 @@ static u16 Get_40Tk_D(u8 k) { - return Tab_40T_k[k]; /* FIXME: k or k<<1 ?*/ + return Tab_40T_k[k]; /* FIXME: k or k << 1 ?*/ } static u16 Get_Fk_D(u8 k) { - return Table_F_k[k]; /* FIXME: k or k<<1 ? */ + return Table_F_k[k]; /* FIXME: k or k << 1 ? */ } @@ -2270,7 +2270,7 @@ if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ - j = i & (1<<0); + j = i & (1 << 0); pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/ pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/ pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */ @@ -3276,7 +3276,7 @@ /* Clear Legacy BIOS Mode bit */ reg = 0x94; val = Get_NB32(dev, reg); - val &= ~(1<<LegacyBiosMode); + val &= ~(1 << LegacyBiosMode); Set_NB32(dev, reg, val); } @@ -3846,11 +3846,11 @@ addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ wrap32dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ + lo |= (1 << 17); /* HWCR.wrap32dis */ + lo &= ~(1 << 15); /* SSEDIS */ /* Setting wrap32dis allows 64-bit memory references in 32bit mode */ _WRMSR(addr, lo, hi); @@ -3878,7 +3878,7 @@ if (!wrap32dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } } diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c index 59618f6..99b0cbc 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c @@ -63,7 +63,7 @@ u32 ret = 0; for (i = 31; i > 0; i--) { - if (x & (1<<i)) { + if (x & (1 << i)) { ret = i; break; } @@ -80,7 +80,7 @@ u32 ret = 32; for (i = 0; i < 32; i++) { - if (x & (1<<i)) { + if (x & (1 << i)) { ret = i; break; } @@ -107,7 +107,7 @@ "outb %%al, $0xed\n\t" /* _EXECFENCE */ "clflush %%fs:(%0)\n\t" "mfence\n\t" - ::"a" (addr_hi<<8) + ::"a" (addr_hi << 8) ); } @@ -285,7 +285,7 @@ "movl %%fs:-64(%%esi), %%eax\n\t" //+1 "movl %%fs:(%%esi), %%eax\n\t" //+2 "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) + :: "a"(0), "S"((addr << 8)+128) ); } @@ -304,7 +304,7 @@ "loop 1b\n\t" "mfence\n\t" - :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf) + :: "a" (addr << 8), "d" (16), "c" (3 * 4), "b"(buf) ); } @@ -323,7 +323,7 @@ "clflush %%fs:(%%esi)\n\t" //+2 "mfence\n\t" - :: "S"((addr<<8)+128) + :: "S"((addr << 8)+128) ); } diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 7140007..ecd8802 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -280,18 +280,18 @@ print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); cr4 = read_cr4(); - if (cr4 & (1<<9)) { + if (cr4 & (1 << 9)) { _SSE2 = 1; } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { + if (lo & (1 << 17)) { _Wrap32Dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ + lo |= (1 << 17); /* HWCR.wrap32dis */ _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ /* Disable ECC correction of reads on the dram bus. */ @@ -370,12 +370,12 @@ if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -602,7 +602,7 @@ */ /* FindDQSDatDimmVal_D is not required since we use an array */ - if (pDCTstat->Status & (1<<SB_Over400MHz)) + if (pDCTstat->Status & (1 << SB_Over400MHz)) dn = ChipSel >> 1; /*if odd or even logical DIMM */ pDCTstat->DQSDelay = @@ -928,17 +928,17 @@ dev = pDCTstat->dev_dct; reg = 0x90; val = Get_NB32(dev, reg); - if (val & (1<<DimmEcEn)) { + if (val & (1 << DimmEcEn)) { _DisableDramECC |= 0x01; - val &= ~(1<<DimmEcEn); + val &= ~(1 << DimmEcEn); Set_NB32(dev, reg, val); } if (!pDCTstat->GangedMode) { reg = 0x190; val = Get_NB32(dev, reg); - if (val & (1<<DimmEcEn)) { + if (val & (1 << DimmEcEn)) { _DisableDramECC |= 0x02; - val &= ~(1<<DimmEcEn); + val &= ~(1 << DimmEcEn); Set_NB32(dev, reg, val); } } @@ -962,13 +962,13 @@ if ((_DisableDramECC & 0x01) == 0x01) { reg = 0x90; val = Get_NB32(dev, reg); - val |= (1<<DimmEcEn); + val |= (1 << DimmEcEn); Set_NB32(dev, reg, val); } if ((_DisableDramECC & 0x02) == 0x02) { reg = 0x190; val = Get_NB32(dev, reg); - val |= (1<<DimmEcEn); + val |= (1 << DimmEcEn); Set_NB32(dev, reg, val); } } diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 9b22c84..2dea737 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -181,7 +181,7 @@ dev = pDCTstat->dev_nbmisc; val = curBase << 8; if (OB_ECCRedir) { - val |= (1<<0); /* enable redirection */ + val |= (1 << 0); /* enable redirection */ } Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */ val = curBase >> 24; diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index 41a479b..fdd508b 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -33,11 +33,11 @@ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); if (mctGet_NVbits(NV_AllMemClks) == 0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ - if (!(pDCTstat->Status & (1<<SB_DiagClks))) { + if (!(pDCTstat->Status & (1 << SB_DiagClks))) { for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; if (val < 8) { - if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { + if (!(pDCTstat->DIMMValidDCT[dct] & (1 << val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); } @@ -45,9 +45,9 @@ } } } - DramTimingLo &= ~(0xff<<24); - DramTimingLo |= NewDramTimingLo & (0xff<<24); - DramTimingLo &= (0x4d<<24); /* FIXME - enable all MemClks for now */ + DramTimingLo &= ~(0xff << 24); + DramTimingLo |= NewDramTimingLo & (0xff << 24); + DramTimingLo &= (0x4d << 24); /* FIXME - enable all MemClks for now */ return DramTimingLo; } @@ -77,7 +77,7 @@ base += HoleSize; base >>= 27 - 8; val = Get_NB32(dev, 0x110); - val &= ~(0xfff<<11); + val &= ~(0xfff << 11); val |= (base & 0xfff)<<11; Set_NB32(dev, 0x110, val); } diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c index b67282e..1af202e 100644 --- a/src/northbridge/amd/amdmct/mct/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct/mcthdi.c @@ -25,6 +25,6 @@ /*flag for selecting HW/SW DRAM Init HW DRAM Init */ reg = 0x90 + 0x100 * dct; /*DRAM Configuration Low */ val = Get_NB32(dev, reg); - val |= (1<<InitDram); + val |= (1 << InitDram); Set_NB32(dev, reg, val); } diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index deb0f8a..f2d355e 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -91,15 +91,15 @@ /* Limit */ /* MtrrAddr */ if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<<GSB_MTRRshort; + pMCTstat->GStatus |= 1 << GSB_MTRRshort; - pMCTstat->Sub4GCacheTop = Cache32bTOP<<8; + pMCTstat->Sub4GCacheTop = Cache32bTOP << 8; /*====================================================================== Set TOP_MEM and TOM2 CPU registers ======================================================================*/ addr = TOP_MEM; - lo = Bottom32bIO<<8; + lo = Bottom32bIO << 8; hi = Bottom32bIO>>24; _WRMSR(addr, lo, hi); print_tx("\t CPUMemTyping: Bottom32bIO:", Bottom32bIO); @@ -115,11 +115,11 @@ addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En = 1 */ - lo |= (1<<22); /* Tom2ForceMemTypeWB */ + lo |= (1 << 21); /* MtrrTom2En = 1 */ + lo |= (1 << 22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En = 0 */ - lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ + lo &= ~(1 << 21); /* MtrrTom2En = 0 */ + lo &= ~(1 << 22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); } @@ -173,7 +173,7 @@ valx += curBase; if ((curBase == 0) || (*pLimit < valx)) { /* flop direction to "descending" code path*/ - valx = 1<<bsr(*pLimit - curBase); + valx = 1 << bsr(*pLimit - curBase); curSize = valx; valx += curBase; } @@ -249,6 +249,6 @@ print_tx("\t UMAMemTyping_D: Cache32bTOP:", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<<GSB_MTRRshort; + pMCTstat->GStatus |= 1 << GSB_MTRRshort; } } diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 0acb6f4..16154d5 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -44,8 +44,8 @@ uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if (!(val & (3<<12))) - val |= 1<<12; + if (!(val & (3 << 12))) + val |= 1 << 12; } return val; } @@ -66,9 +66,9 @@ reg_off = 0x100 * dct; reg = 0x90 + reg_off; /* Dram Configuration Lo */ val = Get_NB32(dev, reg); - val |= 1<<ForceAutoPchg; + val |= 1 << ForceAutoPchg; if (!pDCTstat->GangedMode) - val |= 1<<BurstLength32; + val |= 1 << BurstLength32; Set_NB32(dev, reg, val); reg = 0x88 + reg_off; /* cx = Dram Timing Lo */ @@ -112,7 +112,7 @@ dev = pDCTstat->dev_dct; reg = 0x11c; val = Get_NB32(dev, reg); - val &= ~(1<<PrefDramTrainMode); + val &= ~(1 << PrefDramTrainMode); Set_NB32(dev, reg, val); } } @@ -212,7 +212,7 @@ index_reg = 0x98 + 0x100 * dct; index = 0x0D004201; val = Get_NB32_index_wait(dev, index_reg, index); - value &= ~(1<<27); + value &= ~(1 << 27); value |= ((val >> 10) & 1) << 27; } return value; diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 60857f4..f46c989 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -445,12 +445,12 @@ if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -771,7 +771,7 @@ SetUpperFSbase(addr); addr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { + if ((pDCTstat->Status & (1 << SB_128bitmode)) && channel) { addr += 8; /* second channel */ test_buf += 8; } @@ -782,9 +782,9 @@ print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4); if (value == test_buf[i]) { - pDCTstat->DqsRcvEn_Pass |= (1<<i); + pDCTstat->DqsRcvEn_Pass |= (1 << i); } else { - pDCTstat->DqsRcvEn_Pass &= ~(1<<i); + pDCTstat->DqsRcvEn_Pass &= ~(1 << i); } } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index ab278e9..562954f 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -112,7 +112,7 @@ } } if (!valid) { - pDCTstat->ErrStatus |= 1<<SB_NORCVREN; + pDCTstat->ErrStatus |= 1 << SB_NORCVREN; } else { pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 4c6d8e6..3d57571 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -126,19 +126,19 @@ u32 pattern_buf; cr4 = read_cr4(); - if (cr4 & (1<<9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ + lo |= (1 << 17); /* HWCR.wrap32dis */ + lo &= ~(1 << 15); /* SSEDIS */ /* Setting wrap32dis allows 64-bit memory references in real mode */ _WRMSR(addr, lo, hi); @@ -184,12 +184,12 @@ if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -224,7 +224,7 @@ dev = pDCTstat->dev_dct; reg = 0x78 + Channel * 0x100; val = Get_NB32(dev, reg); - val &= ~(0x3ff<<22); + val &= ~(0x3ff << 22); val |= MaxRdLatVal << 22; /* program MaxRdLatency to correspond with current delay */ Set_NB32(dev, reg, val); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1ac91a1..30520e0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3790,9 +3790,9 @@ for (Channel = 0; Channel < 2; Channel++) { reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); - val &= ~(0x3ff<<22); + val &= ~(0x3ff << 22); val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22); - val &= ~(1<<DqsRcvEnTrain); + val &= ~(1 << DqsRcvEnTrain); Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/ } } @@ -3873,9 +3873,9 @@ limit = pDCTstat->DCTSysLimit; } else if (base == BottomIO) { /* SW Node Hoist */ - pMCTstat->GStatus |= 1<<GSB_SpIntRemapHole; - pDCTstat->Status |= 1<<SB_SWNodeHole; - pMCTstat->GStatus |= 1<<GSB_SoftHole; + pMCTstat->GStatus |= 1 << GSB_SpIntRemapHole; + pDCTstat->Status |= 1 << SB_SWNodeHole; + pMCTstat->GStatus |= 1 << GSB_SoftHole; pMCTstat->HoleBase = base; limit -= base; base = _4GB_RJ8; @@ -4218,7 +4218,7 @@ dev = pDCTstat->dev_dct; val = Get_NB32_DCT(dev, dct, 0x94); - if (val & (1<<MemClkFreqVal)) { + if (val & (1 << MemClkFreqVal)) { mctHookBeforeDramInit(); /* generalized Hook */ if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) mct_DramInit(pMCTstat, pDCTstat, dct); @@ -4616,30 +4616,30 @@ DramTimingLo |= val; val = pDCTstat->Trcd - Bias_TrcdT; - DramTimingLo |= val<<4; + DramTimingLo |= val << 4; val = pDCTstat->Trp - Bias_TrpT; val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val); - DramTimingLo |= val<<7; + DramTimingLo |= val << 7; val = pDCTstat->Trtp - Bias_TrtpT; - DramTimingLo |= val<<10; + DramTimingLo |= val << 10; val = pDCTstat->Tras - Bias_TrasT; - DramTimingLo |= val<<12; + DramTimingLo |= val << 12; val = pDCTstat->Trc - Bias_TrcT; - DramTimingLo |= val<<16; + DramTimingLo |= val << 16; val = pDCTstat->Trrd - Bias_TrrdT; - DramTimingLo |= val<<22; + DramTimingLo |= val << 22; DramTimingHi = 0; /* Dram Timing High init */ val = pDCTstat->Twtr - Bias_TwtrT; - DramTimingHi |= val<<8; + DramTimingHi |= val << 8; val = 2; /* Tref = 7.8us */ - DramTimingHi |= val<<16; + DramTimingHi |= val << 16; val = 0; for (i = 4; i > 0; i--) { @@ -5060,7 +5060,7 @@ DramControl |= val; /* RdPtrInit = 6 for Cx CPU */ if (mctGet_NVbits(NV_CLKHZAltVidC3)) - DramControl |= 1<<16; /* check */ + DramControl |= 1 << 16; /* check */ DramControl |= 0x00002A00; @@ -5158,7 +5158,7 @@ DramTimingLo = Get_NB32_DCT(dev, dct, 0x88); if (mctGet_NVbits(NV_AllMemClks) == 0) { /* Special Jedec SPD diagnostic bit - "enable all clocks" */ - if (!(pDCTstat->Status & (1<<SB_DiagClks))) { + if (!(pDCTstat->Status & (1 << SB_DiagClks))) { const u8 *p; const u32 *q; p = Tab_ManualCLKDis; @@ -5181,7 +5181,7 @@ dword = 0; byte = 0xFF; while (dword < MAX_CS_SUPPORTED) { - if (pDCTstat->CSPresent & (1<<dword)) { + if (pDCTstat->CSPresent & (1 << dword)) { /* re-enable clocks for the enabled CS */ val = p[dword]; byte &= ~val; @@ -5256,7 +5256,7 @@ if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4) byte -= 3; - if (pDCTstat->DIMMValid & (1<<byte)) { + if (pDCTstat->DIMMValid & (1 << byte)) { byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing]; Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */ Cols = byte & 0x7; /* Cols:0b = 9-bit,... */ @@ -5288,7 +5288,7 @@ continue; /* bit no. of CS field in address mapping reg.*/ - dword <<= (ChipSel<<1); + dword <<= (ChipSel << 1); BankAddrReg |= dword; /* Mask value=(2pow(rows+cols+banks+3)-1)>>8, @@ -5306,18 +5306,18 @@ csMask--; /*set ChipSelect population indicator even bits*/ - pDCTstat->CSPresent |= (1<<ChipSel); + pDCTstat->CSPresent |= (1 << ChipSel); if (Ranks >= 2) /*set ChipSelect population indicator odd bits*/ pDCTstat->CSPresent |= 1 << (ChipSel + 1); - reg = 0x60+(ChipSel<<1); /*Dram CS Mask Register */ + reg = 0x60+(ChipSel << 1); /*Dram CS Mask Register */ val = csMask; val &= 0x1FF83FE0; /* Mask out reserved bits.*/ Set_NB32_DCT(dev, dct, reg, val); } else { - if (pDCTstat->DIMMSPDCSE & (1<<ChipSel)) - pDCTstat->CSTestFail |= (1<<ChipSel); + if (pDCTstat->DIMMSPDCSE & (1 << ChipSel)) + pDCTstat->CSTestFail |= (1 << ChipSel); } /* if DIMMValid*/ } /* while ChipSel*/ @@ -5368,35 +5368,35 @@ byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7; if (byte != byte1) { - pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); break; } byte = pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x0f; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Density] & 0x0f; if (byte != byte1) { - pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); break; } byte = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7; byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] & 0x7; if (byte != byte1) { - pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); break; } byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3) & 0x7; byte1 = (pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] >> 3) & 0x7; if (byte != byte1) { - pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); break; } byte = pDCTstat->spd_data.spd_bytes[i][SPD_DMBANKS] & 7; /* #ranks-1 */ byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_DMBANKS] & 7; /* #ranks-1 */ if (byte != byte1) { - pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO); + pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO); break; } @@ -5433,7 +5433,7 @@ if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) { word = pDCTstat->CSPresent; val = bsf(word); - word &= ~(1<<val); + word &= ~(1 << val); if (word) /* Make sure at least two chip-selects are available */ _DSpareEn = 1; @@ -5530,7 +5530,7 @@ static u16 Get_Fk_D(u8 k) { - return Table_F_k[k]; /* FIXME: k or k<<1 ? */ + return Table_F_k[k]; /* FIXME: k or k << 1 ? */ } static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, @@ -5604,7 +5604,7 @@ pDCTstat->ErrCode = SC_StopError; } else { /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/ - pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum; + pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) pDCTstat->DIMMValid |= 1 << i; @@ -5699,7 +5699,7 @@ if (byte == 2) bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/ - j = i & (1<<0); + j = i & (1 << 0); pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/ pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/ pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */ @@ -5757,38 +5757,38 @@ if (RegDIMMPresent != 0) { if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) { /* module type DIMM mismatch (reg'ed, unbuffered) */ - pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM; + pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM; pDCTstat->ErrCode = SC_StopError; } else{ /* all DIMMs are registered */ - pDCTstat->Status |= 1<<SB_Registered; + pDCTstat->Status |= 1 << SB_Registered; } } if (LRDIMMPresent != 0) { if ((LRDIMMPresent ^ pDCTstat->DIMMValid) !=0) { /* module type DIMM mismatch (reg'ed, unbuffered) */ - pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM; + pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM; pDCTstat->ErrCode = SC_StopError; } else{ /* all DIMMs are registered */ - pDCTstat->Status |= 1<<SB_LoadReduced; + pDCTstat->Status |= 1 << SB_LoadReduced; } } if (pDCTstat->DimmECCPresent != 0) { if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) { /* all DIMMs are ECC capable */ - pDCTstat->Status |= 1<<SB_ECCDIMMs; + pDCTstat->Status |= 1 << SB_ECCDIMMs; } } if (pDCTstat->DimmPARPresent != 0) { if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) { /*all DIMMs are Parity capable */ - pDCTstat->Status |= 1<<SB_PARDIMMs; + pDCTstat->Status |= 1 << SB_PARDIMMs; } } } else { /* no DIMMs present or no DIMMs that qualified. */ - pDCTstat->ErrStatus |= 1<<SB_NoDimms; + pDCTstat->ErrStatus |= 1 << SB_NoDimms; pDCTstat->ErrCode = SC_StopError; } @@ -6851,11 +6851,11 @@ /* Clear Legacy BIOS Mode bit */ reg = 0x94; val = Get_NB32_DCT(dev, 0, reg); - val &= ~(1<<LegacyBiosMode); + val &= ~(1 << LegacyBiosMode); Set_NB32_DCT(dev, 0, reg, val); val = Get_NB32_DCT(dev, 1, reg); - val &= ~(1<<LegacyBiosMode); + val &= ~(1 << LegacyBiosMode); Set_NB32_DCT(dev, 1, reg, val); } @@ -7788,7 +7788,7 @@ msr = BU_CFG2; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) - lo &= ~(1<<ClLinesToNbDis); + lo &= ~(1 << ClLinesToNbDis); _WRMSR(msr, lo, hi); } @@ -8048,10 +8048,10 @@ addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ wrap32dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ + lo |= (1 << 17); /* HWCR.wrap32dis */ /* Setting wrap32dis allows 64-bit memory references in 32bit mode */ _WRMSR(addr, lo, hi); @@ -8079,7 +8079,7 @@ if (!wrap32dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c index 82911c0..252ad4e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c @@ -62,7 +62,7 @@ u32 ret = 0; for (i = 31; i > 0; i--) { - if (x & (1<<i)) { + if (x & (1 << i)) { ret = i; break; } @@ -78,7 +78,7 @@ u32 ret = 32; for (i = 0; i < 32; i++) { - if (x & (1<<i)) { + if (x & (1 << i)) { ret = i; break; } @@ -105,7 +105,7 @@ "outb %%al, $0xed\n\t" /* _EXECFENCE */ "clflush %%fs:(%0)\n\t" "mfence\n\t" - ::"a" (addr_hi<<8) + ::"a" (addr_hi << 8) ); } @@ -226,7 +226,7 @@ "movl %%fs:-64(%%esi), %%eax\n\t" /* +1 */ "movl %%fs:(%%esi), %%eax\n\t" /* +2 */ "mfence\n\t" - :: "a"(0), "S"((addr<<8)+128) + :: "a"(0), "S"((addr << 8)+128) ); } @@ -268,7 +268,7 @@ "clflush %%fs:(%%esi)\n\t" /* +2 */ "mfence\n\t" - :: "S"((addr<<8)+128) + :: "S"((addr << 8)+128) ); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 716e419..5e03497 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -49,9 +49,9 @@ ChipSel = 0; /* Find out if current configuration is capable */ while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { - reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */ + reg = 0x40+(ChipSel << 2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); - if (val & (1<<CSEnable)) { + if (val & (1 << CSEnable)) { EnChipSels++; reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */ val = Get_NB32_DCT(dev, dct, reg); @@ -84,14 +84,14 @@ if (DoIntlv) { if (!_CsIntCap) { - pDCTstat->ErrStatus |= 1<<SB_BkIntDis; + pDCTstat->ErrStatus |= 1 << SB_BkIntDis; DoIntlv = 0; } } if (DoIntlv) { val = Tab_int_D[BankEncd]; - if (pDCTstat->Status & (1<<SB_128bitmode)) + if (pDCTstat->Status & (1 << SB_128bitmode)) val++; AddrLoMask = (EnChipSels - 1) << val; @@ -104,7 +104,7 @@ BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) { - reg = 0x40 + (ChipSel<<2); /* Dram CS Base 0 */ + reg = 0x40 + (ChipSel << 2); /* Dram CS Base 0 */ val = Get_NB32_DCT(dev, dct, reg); if (val & 3) { val_lo = val & AddrLoMask; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 10d4206..1f5be60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -425,18 +425,18 @@ print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0); cr4 = read_cr4(); - if (cr4 & (1<<9)) { + if (cr4 & (1 << 9)) { _SSE2 = 1; } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { + if (lo & (1 << 17)) { _Wrap32Dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ + lo |= (1 << 17); /* HWCR.wrap32dis */ _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ /* Disable ECC correction of reads on the dram bus. */ @@ -832,12 +832,12 @@ if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1642,18 +1642,18 @@ print_debug_dqs("\nTrainDQSReceiverEnCyc: Node_ID ", pDCTstat->Node_ID, 0); cr4 = read_cr4(); - if (cr4 & (1<<9)) { + if (cr4 & (1 << 9)) { _SSE2 = 1; } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { + if (lo & (1 << 17)) { _Wrap32Dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ + lo |= (1 << 17); /* HWCR.wrap32dis */ _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */ /* Disable ECC correction of reads on the dram bus. */ @@ -1863,12 +1863,12 @@ if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1891,7 +1891,7 @@ u16 i; buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - if (pDCTstat->Status & (1<<SB_128bitmode)) { + if (pDCTstat->Status & (1 << SB_128bitmode)) { pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */ for (i = 0; i < 16*18; i++) buf[i] = TestPatternJD1b_D[i]; @@ -2222,16 +2222,16 @@ dev = pDCTstat->dev_dct; reg = 0x90; val = Get_NB32_DCT(dev, 0, reg); - if (val & (1<<DimmEcEn)) { + if (val & (1 << DimmEcEn)) { _DisableDramECC |= 0x01; - val &= ~(1<<DimmEcEn); + val &= ~(1 << DimmEcEn); Set_NB32_DCT(dev, 0, reg, val); } if (!pDCTstat->GangedMode) { val = Get_NB32_DCT(dev, 1, reg); - if (val & (1<<DimmEcEn)) { + if (val & (1 << DimmEcEn)) { _DisableDramECC |= 0x02; - val &= ~(1<<DimmEcEn); + val &= ~(1 << DimmEcEn); Set_NB32_DCT(dev, 1, reg, val); } } @@ -2249,12 +2249,12 @@ if ((_DisableDramECC & 0x01) == 0x01) { val = Get_NB32_DCT(dev, 0, 0x90); - val |= (1<<DimmEcEn); + val |= (1 << DimmEcEn); Set_NB32_DCT(dev, 0, 0x90, val); } if ((_DisableDramECC & 0x02) == 0x02) { val = Get_NB32_DCT(dev, 1, 0x90); - val |= (1<<DimmEcEn); + val |= (1 << DimmEcEn); Set_NB32_DCT(dev, 1, 0x90, val); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c index 2038af9..32d99ce 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c @@ -28,6 +28,6 @@ /*flag for selecting HW/SW DRAM Init HW DRAM Init */ reg = 0x90; /*DRAM Configuration Low */ val = Get_NB32_DCT(dev, dct, reg); - val |= (1<<InitDram); + val |= (1 << InitDram); Set_NB32_DCT(dev, dct, reg, val); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 8a1f736..11f4877 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -95,15 +95,15 @@ /* Limit */ /* MtrrAddr */ if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<<GSB_MTRRshort; + pMCTstat->GStatus |= 1 << GSB_MTRRshort; - pMCTstat->Sub4GCacheTop = Cache32bTOP<<8; + pMCTstat->Sub4GCacheTop = Cache32bTOP << 8; /*====================================================================== Set TOP_MEM and TOM2 CPU registers ======================================================================*/ addr = TOP_MEM; - lo = Bottom32bIO<<8; + lo = Bottom32bIO << 8; hi = Bottom32bIO>>24; _WRMSR(addr, lo, hi); printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom32bIO:%x\n", Bottom32bIO); @@ -117,11 +117,11 @@ addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En = 1 */ - lo |= (1<<22); /* Tom2ForceMemTypeWB */ + lo |= (1 << 21); /* MtrrTom2En = 1 */ + lo |= (1 << 22); /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En = 0 */ - lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ + lo &= ~(1 << 21); /* MtrrTom2En = 0 */ + lo &= ~(1 << 22); /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); } @@ -173,7 +173,7 @@ valx += curBase; if ((curBase == 0) || (*pLimit < valx)) { /* flop direction to "descending" code path*/ - valx = 1<<bsr(*pLimit - curBase); + valx = 1 << bsr(*pLimit - curBase); curSize = valx; valx += curBase; } @@ -250,6 +250,6 @@ printk(BIOS_DEBUG, "\t UMAMemTyping_D: Cache32bTOP:%x\n", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); if (addr == -1) /* ran out of MTRRs?*/ - pMCTstat->GStatus |= 1<<GSB_MTRRshort; + pMCTstat->GStatus |= 1 << GSB_MTRRshort; } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 984f604..2776051 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -579,7 +579,7 @@ SetUpperFSbase(testaddr); testaddr <<= 8; - if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) { + if ((pDCTstat->Status & (1 << SB_128bitmode)) && channel) { testaddr += 8; /* second channel */ } @@ -997,12 +997,12 @@ if (!_Wrap32Dis) { msr = rdmsr(HWCR); - msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + msr.lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ wrmsr(HWCR, msr); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1500,12 +1500,12 @@ if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -1720,12 +1720,12 @@ if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 2592eed..5853fd2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -81,7 +81,7 @@ p[i] = val; } - /* pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); */ + /* pDCTstat->DimmTrainFail &= ~(1 << Receiver+Channel); */ return MaxValue; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index 8eeb93f..29dccf6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -106,7 +106,7 @@ } } if (!valid) { - pDCTstat->ErrStatus |= 1<<SB_NORCVREN; + pDCTstat->ErrStatus |= 1 << SB_NORCVREN; } else { pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 039a747..46c59ea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -125,19 +125,19 @@ u32 pattern_buf; cr4 = read_cr4(); - if (cr4 & (1<<9)) { /* save the old value */ + if (cr4 & (1 << 9)) { /* save the old value */ _SSE2 = 1; } - cr4 |= (1<<9); /* OSFXSR enable SSE2 */ + cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); - if (lo & (1<<17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } - lo |= (1<<17); /* HWCR.wrap32dis */ - lo &= ~(1<<15); /* SSEDIS */ + lo |= (1 << 17); /* HWCR.wrap32dis */ + lo &= ~(1 << 15); /* SSEDIS */ /* Setting wrap32dis allows 64-bit memory references in real mode */ _WRMSR(addr, lo, hi); @@ -183,12 +183,12 @@ if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); - lo &= ~(1<<17); /* restore HWCR.wrap32dis */ + lo &= ~(1 << 17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if (!_SSE2) { cr4 = read_cr4(); - cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ + cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */ write_cr4(cr4); } @@ -222,8 +222,8 @@ dev = pDCTstat->dev_dct; reg = 0x78; val = Get_NB32_DCT(dev, Channel, reg); - val &= ~(0x3ff<<22); - val |= MaxRdLatVal<<22; + val &= ~(0x3ff << 22); + val |= MaxRdLatVal << 22; /* program MaxRdLatency to correspond with current delay */ Set_NB32_DCT(dev, Channel, reg, val); } @@ -242,7 +242,7 @@ u8 ret = DQS_PASS; SetUpperFSbase(addr); - addr_lo = addr<<8; + addr_lo = addr << 8; _EXECFENCE; for (i = 0; i < 16*3; i++) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index 53c4a2d..b16121f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -480,7 +480,7 @@ while (reg < 0x60) { val = Get_NB32_DCT(pDCTstat->dev_dct, dct, reg); if (val & (1 << CSEnable)) - set ? (val |= 1 << onDimmMirror) : (val &= ~(1<<onDimmMirror)); + set ? (val |= 1 << onDimmMirror) : (val &= ~(1 << onDimmMirror)); Set_NB32_DCT(pDCTstat->dev_dct, dct, reg, val); reg += 8; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index f17e4d6..aa68c93 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -44,7 +44,7 @@ AmdMemPCIRead(loc, pValue); *pValue = *pValue >> lowbit; /* Shift */ - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ + /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */ if ((highbit-lowbit) != 31) *pValue &= (((u32)1 << (highbit-lowbit+1))-1); } @@ -55,7 +55,7 @@ /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */ - /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */ + /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */ if ((highbit-lowbit) != 31) mask = (((u32)1 << (highbit-lowbit+1))-1); else diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 93ec350..ae8110d 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -35,16 +35,16 @@ /* here is programming for the various MSRs.*/ #define IM_QWAIT 0x100000 -#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ +#define DMCF_WRITE_SERIALIZE_REQUEST (2 << 12) /* 2 outstanding */ /* in high */ #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ /* these are the 8-bit attributes for controlling RCONF registers */ -#define CACHE_DISABLE (1<<0) -#define WRITE_ALLOCATE (1<<1) -#define WRITE_PROTECT (1<<2) -#define WRITE_THROUGH (1<<3) -#define WRITE_COMBINE (1<<4) -#define WRITE_SERIALIZE (1<<5) +#define CACHE_DISABLE (1 << 0) +#define WRITE_ALLOCATE (1 << 1) +#define WRITE_PROTECT (1 << 2) +#define WRITE_THROUGH (1 << 3) +#define WRITE_COMBINE (1 << 4) +#define WRITE_SERIALIZE (1 << 5) /* RAM has none of this stuff */ #define RAM_PROPERTIES (0) @@ -56,17 +56,17 @@ /* the are region configuration range registers, or RRCF */ /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */ /* so no left-shift needed for top or base */ -#define RRCF_LOW(base,properties) (base|(1<<8)|properties) +#define RRCF_LOW(base,properties) (base|(1 << 8)|properties) #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE) /* build initializer for P2D MSR */ -#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}} -#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}} -#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} -#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} -#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} +#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(pbase>>24), .lo=(pbase << 8)|pmask}} +#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(poffset << 8)|(pbase>>24), .lo=(pbase << 8)|pmask}} +#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(pmax>>12), .lo=(pmax << 20)|pmin}} +#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(poffset << 8)|(pmax>>12), .lo=(pmax << 20)|pmin}} +#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(wen), .lo=(ren << 16)|(pscbase>>18)}} +#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(ibase>>12), .lo=(ibase << 20)|imask}} +#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1 << 29)|(bizarro << 28), .lo=(en << 24)|(wen << 21)|(ren << 20)|(ibase << 3)}} void print_conf(void); void graphics_init(void); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 5ba0e44..3cd84d5 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -72,12 +72,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -87,10 +87,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -100,7 +100,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -171,7 +171,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -660,7 +660,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index bd4884c..899ed0d 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -99,7 +99,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -178,7 +178,7 @@ { u32 val; - val = 1 | (nodeid << 4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -663,7 +663,7 @@ hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { /* we find the hole */ - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index f8be67d..a912ec4 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -99,7 +99,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i=0; i<nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -178,7 +178,7 @@ { u32 val; - val = 1 | (nodeid << 4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -664,7 +664,7 @@ hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { /* we find the hole */ - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 960078e..4d01dda 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -67,12 +67,12 @@ temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; + d.mask |= temp << 21; temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] d.mask |= (temp & 1); // enable bit d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; + d.base |= temp << 21; return d; } @@ -82,10 +82,10 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for (i = 0; i < node_nums; i++) pci_write_config32(__f1_dev[i], reg, tempreg); } @@ -95,7 +95,7 @@ u32 i; u32 tempreg; /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit for (i = 0; i < nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); @@ -174,7 +174,7 @@ { u32 val; - val = 1 | (nodeid<<4) | (linkn<<12); + val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing * (1)mmio 0xa0000:0xbffff * (2)io 0x3b0:0x3bb, 0x3c0:0x3df @@ -676,7 +676,7 @@ if (!(d.mask & 1)) continue; // no memory on this node hole = pci_read_config32(__f1_dev[i], 0xf0); if (hole & 2) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole break; // only one hole } diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 9c9171d..c3dc70a 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -50,17 +50,17 @@ #define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ // CAS# Latency bits in the DRAM Timing (DRT) register -#define DRT_CAS_2_5 (0<<4) -#define DRT_CAS_2_0 (1<<4) -#define DRT_CAS_MASK (3<<4) +#define DRT_CAS_2_5 (0 << 4) +#define DRT_CAS_2_0 (1 << 4) +#define DRT_CAS_MASK (3 << 4) // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register -#define RAM_COMMAND_NOP (1<<4) -#define RAM_COMMAND_PRECHARGE (2<<4) -#define RAM_COMMAND_MRS (3<<4) -#define RAM_COMMAND_EMRS (4<<4) -#define RAM_COMMAND_CBR (6<<4) -#define RAM_COMMAND_NORMAL (7<<4) +#define RAM_COMMAND_NOP (1 << 4) +#define RAM_COMMAND_PRECHARGE (2 << 4) +#define RAM_COMMAND_MRS (3 << 4) +#define RAM_COMMAND_EMRS (4 << 4) +#define RAM_COMMAND_CBR (6 << 4) +#define RAM_COMMAND_NORMAL (7 << 4) #define DRC_DONE (1 << 29) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index b38132a..1d5ab6e 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1827,14 +1827,14 @@ pci_write_config8(MCHDEV, PAM_0 + i, 0x33); /* Conservatively say each row has 64MB of ram, we will fix this up later - * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13 + * Initial TOLM 8 rows 64MB each (1 << 3 * 1 << 26) >> 16 = 1 << 13 * * FIXME: Hard-coded limit to first four rows to prevent overlap! */ pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201); pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404); //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605); - pci_write_config16(MCHDEV, TOLM, (1<<13)); + pci_write_config16(MCHDEV, TOLM, (1 << 13)); /* DIMM clocks off */ pci_write_config8(MCHDEV, CKDIS, 0xff); @@ -1846,7 +1846,7 @@ // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. dword = pci_read_config32(MCHDEV, DRT); dword &= 0xC7F8FFFF; - dword |= (0x28<<24)|(0x03<<16); + dword |= (0x28 << 24)|(0x03 << 16); pci_write_config32(MCHDEV, DRT, dword); dword = pci_read_config32(MCHDEV, DRC); diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 77aba94..f25347a 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -57,7 +57,7 @@ void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0); /* clear GTT, 2MB is enough (and should be safe) */ - memset(bar, 0, 2<<20); + memset(bar, 0, 2 << 20); /* and now disable again */ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 7a3b498..af4cf5c 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -215,9 +215,9 @@ } if (stepping > STEPPING_B0) { if (fsb != FSB_CLOCK_667MHz) - MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)) | (1 << 21); + MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3 << 21)) | (1 << 21); else - MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)); + MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3 << 21)); } if (stepping > STEPPING_B2) MCHBAR32(0x44) |= 1 << 30; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d2da3b0..df756e1 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1467,14 +1467,14 @@ "system-memory i/o initialization.\n"); tmp = MCHBAR32(0x1400); - tmp &= ~(3<<13); - tmp |= (1<<9) | (1<<13); + tmp &= ~(3 << 13); + tmp |= (1 << 9) | (1 << 13); MCHBAR32(0x1400) = tmp; tmp = MCHBAR32(0x140c); - tmp &= ~(0xff | (1<<11) | (1<<12) | - (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); - tmp |= (1<<7) | (1<<11) | (1<<16); + tmp &= ~(0xff | (1 << 11) | (1 << 12) | + (1 << 16) | (1 << 18) | (1 << 27) | (0xf << 28)); + tmp |= (1 << 7) | (1 << 11) | (1 << 16); switch (ddr3clock) { case MEM_CLOCK_667MT: tmp |= 9 << 28; @@ -1491,8 +1491,8 @@ MCHBAR32(0x1440) &= ~1; tmp = MCHBAR32(0x1414); - tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); - tmp |= (3<<11); + tmp &= ~((1 << 20) | (7 << 11) | (0xf << 24) | (0xf << 16)); + tmp |= (3 << 11); switch (ddr3clock) { case MEM_CLOCK_667MT: tmp |= (2 << 24) | (10 << 16); @@ -1506,11 +1506,11 @@ } MCHBAR32(0x1414) = tmp; - MCHBAR32(0x1418) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); + MCHBAR32(0x1418) &= ~((1 << 3) | (1 << 11) | (1 << 19) | (1 << 27)); - MCHBAR32(0x141c) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); + MCHBAR32(0x141c) &= ~((1 << 3) | (1 << 11) | (1 << 19) | (1 << 27)); - MCHBAR32(0x1428) |= 1<<14; + MCHBAR32(0x1428) |= 1 << 14; tmp = MCHBAR32(0x142c); tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a8c8015..79434b3 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -202,7 +202,7 @@ uint64_t mask; /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + mask = ((1ULL << 20)-1); mask = ~mask; value = 0; diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c index 6af7b9b..d39593f 100644 --- a/src/northbridge/intel/i3100/memory_initialized.c +++ b/src/northbridge/intel/i3100/memory_initialized.c @@ -20,5 +20,5 @@ { u32 drc; drc = pci_read_config32(NB_DEV, DRC); - return (drc & (1<<29)); + return (drc & (1 << 29)); } diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index 3f4939c..3bad28c 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -49,15 +49,15 @@ do { val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ + if ((val & (1 << 10)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); + pci_write_config16(dev, 0x74, (ctl | (1 << 5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag = 1; hard_reset(); } - } while (val & (3<<10)); + } while (val & (3 << 10)); pciexp_scan_bridge(dev); } diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 62f485d..df755e7 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -42,8 +42,8 @@ printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n"); val = pci_read_config16(dev, 0x66); - val &= ~(1<<8); - val |= 1<<8; + val &= ~(1 << 8); + val |= 1 << 8; pci_write_config16(dev, 0x66, val); /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */ @@ -71,15 +71,15 @@ do { val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<11)) && (!flag)) { /* training error */ + if ((val & (1 << 11)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); + pci_write_config16(dev, 0x74, (ctl | (1 << 5))); val = pci_read_config16(dev, 0x76); printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag = 1; hard_reset(); } - } while (val & (3<<10)); + } while (val & (3 << 10)); pciexp_scan_bridge(dev); } diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index aebe4e8..edadbb9 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -54,7 +54,7 @@ PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, /* 0xf4 */ - PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, + PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1 << 22)|(6 << 2) | DEVPRES1_CONFIG, /* 0x14 */ PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0), @@ -309,9 +309,9 @@ break; } - drt |= (1<<6); /* back to back write turn around */ + drt |= (1 << 6); /* back to back write turn around */ - drt |= (3<<18); /* Trasmax */ + drt |= (3 << 18); /* Trasmax */ for (cnt = 0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { @@ -355,22 +355,22 @@ reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff; if (((index>>16) & 0x0ff) < reg) { index &= ~(0x0ff << 16); - index |= (reg<<16); + index |= (reg << 16); } reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff; if (((index2>>0) & 0x0ff) < reg) { index2 &= ~(0x0ff << 0); - index2 |= (reg<<0); + index2 |= (reg << 0); } reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff; if (((index2>>8) & 0x0ff) < reg) { index2 &= ~(0x0ff << 8); - index2 |= (reg<<8); + index2 |= (reg << 8); } reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff; if (((index2>>16) & 0x0ff) < reg) { index2 &= ~(0x0ff << 16); - index2 |= (reg<<16); + index2 |= (reg << 16); } } @@ -378,151 +378,151 @@ value = cycle_time[drc & 3]; if (value <= 0x50) { /* 200 MHz */ if ((index & 7) > 2) { - drt |= (2<<2); /* CAS latency 4 */ + drt |= (2 << 2); /* CAS latency 4 */ cas_latency = 40; } else { - drt |= (1<<2); /* CAS latency 3 */ + drt |= (1 << 2); /* CAS latency 3 */ cas_latency = 30; } if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ + drt |= (1 << 8); /* Trp RAS Precharge */ } else { - drt |= (2<<8); /* Trp RAS Precharge */ + drt |= (2 << 8); /* Trp RAS Precharge */ } /* Trcd RAS to CAS delay */ if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); + drt |= (0 << 10); } else { - drt |= (1<<10); + drt |= (1 << 10); } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); + drt |= (1 << 12); /* Trc TRS min */ if ((index2 & 0x0ff00) <= 0x03700) - drt |= (0<<14); + drt |= (0 << 14); else if ((index2 & 0xff00) <= 0x03c00) - drt |= (1<<14); + drt |= (1 << 14); else - drt |= (2<<14); /* spd 41 */ + drt |= (2 << 14); /* spd 41 */ - drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ + drt |= (2 << 16); /* Twr not defined for DDR docs say use 2 */ /* Trrd Row Delay */ if ((index & 0x0ff0000) <= 0x0140000) { - drt |= (0<<20); + drt |= (0 << 20); } else if ((index & 0x0ff0000) <= 0x0280000) { - drt |= (1<<20); + drt |= (1 << 20); } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (2<<20); + drt |= (2 << 20); } else { - drt |= (3<<20); + drt |= (3 << 20); } /* Trfc Auto refresh cycle time */ if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); + drt |= (0 << 22); } else if ((index2 & 0x0ff0000) <= 0x0690000) { - drt |= (1<<22); + drt |= (1 << 22); } else { - drt |= (2<<22); + drt |= (2 << 22); } /* Docs say use 55 for all 200MHz */ - drt |= (0x055<<24); + drt |= (0x055 << 24); } else if (value <= 0x60) { /* 167 MHz */ /* according to new documentation CAS latency is 00 * for bits 3:2 for all 167 MHz drt |= ((index & 3)<<2); */ /* set CAS latency */ if ((index & 0x0ff00) <= 0x03000) { - drt |= (1<<8); /* Trp RAS Precharge */ + drt |= (1 << 8); /* Trp RAS Precharge */ } else { - drt |= (2<<8); /* Trp RAS Precharge */ + drt |= (2 << 8); /* Trp RAS Precharge */ } /* Trcd RAS to CAS delay */ if ((index2 & 0x0ff) <= 0x030) { - drt |= (0<<10); + drt |= (0 << 10); } else { - drt |= (1<<10); + drt |= (1 << 10); } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); + drt |= (2 << 12); /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ + drt |= (2 << 14); /* spd 41, but only one choice */ - drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ + drt |= (2 << 16); /* Twr not defined for DDR docs say 2 */ /* Trrd Row Delay */ if ((index & 0x0ff0000) <= 0x0180000) { - drt |= (0<<20); + drt |= (0 << 20); } else if ((index & 0x0ff0000) <= 0x0300000) { - drt |= (1<<20); + drt |= (1 << 20); } else { - drt |= (2<<20); + drt |= (2 << 20); } /* Trfc Auto refresh cycle time */ if ((index2 & 0x0ff0000) <= 0x0480000) { - drt |= (0<<22); + drt |= (0 << 22); } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); + drt |= (2 << 22); } else { - drt |= (2<<22); + drt |= (2 << 22); } /* Docs state to use 99 for all 167 MHz */ - drt |= (0x099<<24); + drt |= (0x099 << 24); } else if (value <= 0x75) { /* 133 MHz */ drt |= ((index & 3)<<2); /* set CAS latency */ if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ + drt |= (1 << 8); /* Trp RAS Precharge */ } else { - drt |= (2<<8); /* Trp RAS Precharge */ + drt |= (2 << 8); /* Trp RAS Precharge */ } /* Trcd RAS to CAS delay */ if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); + drt |= (0 << 10); } else { - drt |= (1<<10); + drt |= (1 << 10); } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); + drt |= (1 << 12); /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ + drt |= (2 << 14); /* spd 41, but only one choice */ - drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ + drt |= (1 << 16); /* Twr not defined for DDR docs say 1 */ /* Trrd Row Delay */ if ((index & 0x0ff0000) <= 0x01e0000) { - drt |= (0<<20); + drt |= (0 << 20); } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (1<<20); + drt |= (1 << 20); } else { - drt |= (2<<20); + drt |= (2 << 20); } /* Trfc Auto refresh cycle time */ if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); + drt |= (0 << 22); } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); + drt |= (2 << 22); } else { - drt |= (2<<22); + drt |= (2 << 22); } /* Based on CAS latency */ if (index & 7) - drt |= (0x099<<24); + drt |= (0x099 << 24); else - drt |= (0x055<<24); + drt |= (0x055 << 24); } else { @@ -693,7 +693,7 @@ for (i = 0; i < 1001; i++) { data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) + if (!(data32 & (1 << 31))) break; } } @@ -725,7 +725,7 @@ for (i = 0; i < 1001; i++) { data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) + if (!(data32 & (1 << 31))) break; } if (i >= 1000) @@ -753,7 +753,7 @@ work32l = dcal_data32_1,work32h = dcal_data32_3; (i < 4) && bit; i++) { for (;;bit--,cnt--) { - if (work32l & (1<<cnt)) + if (work32l & (1 << cnt)) break; if (!cnt) { work32l = dcal_data32_0; @@ -763,7 +763,7 @@ if (!bit) break; } for (;;bit--,cnt--) { - if (!(work32l & (1<<cnt))) + if (!(work32l & (1 << cnt))) break; if (!cnt) { work32l = dcal_data32_0; @@ -776,7 +776,7 @@ break; } data32 = ((bit%8) << 1); - if (work32h & (1<<cnt)) + if (work32h & (1 << cnt)) data32 += 1; if (data32 < 4) { if (!edge) { @@ -808,10 +808,10 @@ recen = recen>>2; for (cnt = 5; cnt < 24;) { for (;; cnt++) - if (!(work32l & (1<<cnt))) + if (!(work32l & (1 << cnt))) break; for (;; cnt++) { - if (work32l & (1<<cnt)) + if (work32l & (1 << cnt)) break; } data32 = (((cnt-1)%8)<<1); @@ -866,16 +866,16 @@ if (cnt > 1) { for (i = 0; i < 32; i+=8) { if (((recena>>i)&0x0f)>7) { - recena &= ~(0x0f<<i); - recena |= (7<<i); + recena &= ~(0x0f << i); + recena |= (7 << i); } } } else { for (i = 0; i < 32; i+=8) { if (((recena>>i)&0x0f)<8) { - recena &= ~(0x0f<<i); - recena |= (8<<i); + recena &= ~(0x0f << i); + recena |= (8 << i); } } } @@ -895,16 +895,16 @@ if (cnt > 1) { for (i = 0; i < 32; i+=8) { if (((recenb>>i)&0x0f)>7) { - recenb &= ~(0x0f<<i); - recenb |= (7<<i); + recenb &= ~(0x0f << i); + recenb |= (7 << i); } } } else { for (i = 0; i < 32; i+=8) { if (((recenb>>8)&0x0f)<8) { - recenb &= ~(0x0f<<i); - recenb |= (8<<i); + recenb &= ~(0x0f << i); + recenb |= (8 << i); } } } @@ -1016,8 +1016,8 @@ /* Apply NOP */ do_delay(); - write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); - write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); + write32(MCBAR+DCALCSR, (0x01000000 | (i << 20))); + write32(MCBAR+DCALCSR, (0x81000000 | (i << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); @@ -1027,7 +1027,7 @@ do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); + write32(MCBAR + DCALCSR, (0x81000000 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1036,7 +1036,7 @@ do_delay(); for (cs = 0; cs < 8; cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000002 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1046,7 +1046,7 @@ for (cs = 0; cs < 8; cs+=2) { /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1058,7 +1058,7 @@ mode_reg = 0x054a0000; for (cs = 0; cs < 8; cs+=2) { write32(MCBAR+DCALADDR, mode_reg); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1069,7 +1069,7 @@ do_delay(); for (cs = 0; cs < 8; cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000002 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1077,47 +1077,47 @@ /* Do 2 refreshes */ do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); + write32(MCBAR+DCALADDR, (mode_reg & ~(1 << 24))); + write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1126,7 +1126,7 @@ do_delay(); for (cs = 0; cs < 8; cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1161,7 +1161,7 @@ } for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); + write32(MCBAR+DCALCSR, (0x810831d8 | (cs << 20))); do data32 = read32(MCBAR+DCALCSR); while (data32 & 0x80000000); } @@ -1174,7 +1174,7 @@ printk(BIOS_DEBUG, "Waiting for mem complete\n"); while (1) { data32 = pci_read_config32(ctrl->f0, 0x98); - if ( (data32 & (1<<31)) == 0) + if ( (data32 & (1 << 31)) == 0) break; } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index fa557da..bbd8237 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -604,7 +604,7 @@ udelay(16); for (cs = 0; cs < 2; cs++) { printk(BIOS_DEBUG, "MRS CS%d\n", cs); - write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); + write32(BAR+DCALADDR, (mode_reg & ~(1 << 24))); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); do data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000); @@ -656,10 +656,10 @@ /* Clear memory and init ECC */ for (cs = 0; cs < 2; cs++) { - if (!(mask & (1<<cs))) + if (!(mask & (1 << cs))) continue; printk(BIOS_DEBUG, "clear memory CS%d\n", cs); - write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); + write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0 << 16)); do data32 = read32(BAR+MBCSR); while (data32 & 0x80000000); if (data32 & 0x40000000) @@ -668,9 +668,9 @@ /* Clear read/write FIFO pointers */ printk(BIOS_DEBUG, "clear read/write fifo pointers\n"); - write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15)); + write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1 << 15)); udelay(16); - write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15)); + write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1 << 15)); udelay(16); dump_dcal_regs(); diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c index 7ccc1a6..f77de3c 100644 --- a/src/northbridge/intel/i82830/memory_initialized.c +++ b/src/northbridge/intel/i82830/memory_initialized.c @@ -22,5 +22,5 @@ { u32 drc; drc = pci_read_config32(NB_DEV, DRC); - return (drc & (1<<29)); + return (drc & (1 << 29)); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 3c5cee5..104b958 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -37,10 +37,10 @@ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) -#define DISPPLANE_BGRX888 (0x6<<26) +#define DISPPLANE_BGRX888 (0x6 << 26) #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) +#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b4c7d13..d311958 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -70,7 +70,7 @@ u32 reg32; reg32 = MCHBAR32(DCC); - reg32 &= ~((3<<21) | (1<<20) | (1<<19) | (7 << 16)); + reg32 &= ~((3 << 21) | (1 << 20) | (1 << 19) | (7 << 16)); reg32 |= command; /* Also set Init Complete */ @@ -248,8 +248,8 @@ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (reg8 & ((1<<7)|(1<<2))) { - if (reg8 & (1<<2)) { + if (reg8 & ((1 << 7)|(1 << 2))) { + if (reg8 & (1 << 2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); @@ -257,9 +257,9 @@ } - if (reg8 & (1<<7)) { + if (reg8 & (1 << 7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); - reg8 &= ~(1<<7); + reg8 &= ~(1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); do_reset = 1; } @@ -279,7 +279,7 @@ /* Set DRAM initialization bit in ICH7 */ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - reg8 |= (1<<7); + reg8 |= (1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); /* clear self refresh status if check is disabled or not a resume */ @@ -289,12 +289,12 @@ /* Validate self refresh config */ if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && - !(MCHBAR8(SLFRCS) & (1<<0))) { + !(MCHBAR8(SLFRCS) & (1 << 0))) { do_reset = 1; } if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && - !(MCHBAR8(SLFRCS) & (1<<1))) { + !(MCHBAR8(SLFRCS) & (1 << 1))) { do_reset = 1; } } @@ -2065,7 +2065,7 @@ /* Gate graphics hardware for frequency change */ reg8 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC + 1); - reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */ + reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */ pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); /* Get graphics frequency capabilities */ @@ -2142,7 +2142,7 @@ /* Graphics Core Display Clock */ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC); - reg8 &= ~((1<<7) | (7<<4)); + reg8 &= ~((1 << 7) | (7 << 4)); if (voltage == VOLTAGE_1_05) { reg8 |= CDCLK_200MHz; @@ -2155,7 +2155,7 @@ reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1); - reg8 |= (1<<3) | (1<<1); + reg8 |= (1 << 3) | (1 << 1); pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8); reg8 |= 0x0f; diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 8bf685d..2fc26e7 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -71,9 +71,9 @@ for (idx = 0; idx < TOTAL_DIMMS; ++idx) #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) -#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) -#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) -#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0)) +#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx << 1].card_type == 0xf) || (dimms[(idx << 1) + 1].card_type == 0xf)) +#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0)) #define FOR_EACH_CHANNEL(idx) \ for (idx = 0; idx < TOTAL_CHANNELS; ++idx) #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ @@ -92,10 +92,10 @@ static bool rank_is_populated(struct dimminfo dimms[], u8 ch, u8 r) { - return ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) - || (dimms[(ch<<1) + 1].card_type + return ((dimms[ch << 1].card_type && ((r) < dimms[ch << 1].ranks)) + || (dimms[(ch << 1) + 1].card_type && ((r) >= 2) - && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))); + && ((r) < (dimms[(ch << 1) + 1].ranks + 2)))); } static inline void barrier(void) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ab6e592..54570b2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -145,7 +145,7 @@ #define MAX_CAS 18 #define MIN_CAS 4 -#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) +#define MAKE_ERR ((channel << 16)|(slotrank << 8)|1) #define GET_ERR_CHANNEL(x) (x>>16) #define MC_BIOS_REQ 0x5e00 diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index a4a830d..4d10549 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1118,7 +1118,7 @@ MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; - rubbish = read32((void *)((val<<3) | addr)); + rubbish = read32((void *)((val << 3) | addr)); udelay(10); MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; @@ -1582,8 +1582,8 @@ rankpop0 = 0; rankpop1 = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED - && (r) < s->dimms[ch<<1].ranks) + if (s->dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED + && (r) < s->dimms[ch << 1].ranks) i = ch << 1; else i = (ch << 1) + 1; @@ -1616,8 +1616,8 @@ // DRB FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED - && (r) < s->dimms[ch<<1].ranks) + if (s->dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED + && (r) < s->dimms[ch << 1].ranks) i = ch << 1; else i = (ch << 1) + 1; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7d8f5cc..4c16d17 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -165,14 +165,14 @@ #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \ FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx) #define CHANNEL_IS_POPULATED(dimms, idx) \ - ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) + ((dimms[idx << 1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx << 1) + 1].card_type != RAW_CARD_UNPOPULATED)) #define CHANNEL_IS_CARDF(dimms, idx) \ - ((dimms[idx<<1].card_type == 0xf) \ - || (dimms[(idx<<1) + 1].card_type == 0xf)) + ((dimms[idx << 1].card_type == 0xf) \ + || (dimms[(idx << 1) + 1].card_type == 0xf)) #define IF_CHANNEL_POPULATED(dimms, idx) \ - if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \ - || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) + if ((dimms[idx << 1].card_type != RAW_CARD_UNPOPULATED) \ + || (dimms[(idx << 1) + 1].card_type != RAW_CARD_UNPOPULATED)) #define FOR_EACH_CHANNEL(idx) \ for (idx = 0; idx < TOTAL_CHANNELS; ++idx) #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ @@ -180,13 +180,13 @@ #define RANKS_PER_CHANNEL 4 #define RANK_IS_POPULATED(dimms, ch, r) \ - (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ - ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) + (((dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch << 1].ranks)) || \ + ((dimms[(ch << 1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch << 1) + 1].ranks + 2)))) #define IF_RANK_POPULATED(dimms, ch, r) \ - if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) < dimms[ch<<1].ranks)) \ - || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \ - && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) + if (((dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) < dimms[ch << 1].ranks)) \ + || ((dimms[(ch << 1) + 1].card_type != RAW_CARD_UNPOPULATED) \ + && ((r) >= 2) && ((r) < (dimms[(ch << 1) + 1].ranks + 2)))) #define FOR_EACH_RANK_IN_CHANNEL(r) \ for (r = 0; r < RANKS_PER_CHANNEL; ++r) #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: cpu/*: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20397 ) Change subject: cpu/*: Add whitespace around '<<' ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56364/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11956/ : SUCCESS -- To view, visit https://review.coreboot.org/20397 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Gerrit-Change-Number: 20397 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 21:02:10 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/kahlee: Add trackpad SMBIOS information
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20311 ) Change subject: google/kahlee: Add trackpad SMBIOS information ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/11952/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/56363/ : SUCCESS -- To view, visit https://review.coreboot.org/20311 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5920f91eac06fa74056dab8bee789c1513c425fa Gerrit-Change-Number: 20311 Gerrit-PatchSet: 6 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 20:59:26 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: cpu/*: Add whitespace around '<<'
by HAOUAS Elyes (Code Review) 27 Jun '17

27 Jun '17

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/20397 Change subject: cpu/*: Add whitespace around '<<' ...................................................................... cpu/*: Add whitespace around '<<' Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/cache_as_ram.inc M src/cpu/amd/agesa/cache_as_ram_legacy.inc M src/cpu/amd/dualcore/amd_sibling.c M src/cpu/amd/dualcore/dualcore.c M src/cpu/amd/dualcore/dualcore_id.c M src/cpu/amd/geode_gx2/cpubug.c M src/cpu/amd/mtrr/amd_mtrr.c M src/cpu/amd/pi/cache_as_ram.inc M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/intel/car/cache_as_ram_ht.inc M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/cpu/via/c7/c7_init.c M src/cpu/via/nano/nano_init.c 14 files changed, 28 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20397/1 diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 857873a..8038177 100644 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -40,7 +40,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 post_code(0xa1) diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc index c0a69ec..5548007 100644 --- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc +++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc @@ -43,7 +43,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 /* Get the cpu_init_detected */ diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index 1c003c8..693ceb8 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -59,7 +59,7 @@ uint32_t val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } @@ -84,7 +84,7 @@ if (bsp_apic_id > 0) { // IOAPIC could start from 0 return 0; - } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 + } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0 return 1; } diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 83302ca..1f25668 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -48,11 +48,11 @@ uint32_t dword; // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); - dword |= 1<<27; // NbMcaToMstCpuEn bit + dword |= 1 << 27; // NbMcaToMstCpuEn bit pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword); // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68); - dword |= 1<<5; + dword |= 1 << 5; pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword); } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 80ce1c7..e7af552 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -43,14 +43,14 @@ // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<<CORE_ID_BIT)-1); + id.coreid &= ((1 << CORE_ID_BIT)-1); } else { // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1<<NODE_ID_BIT)-1); + id.nodeid &= ((1 << NODE_ID_BIT)-1); } return id; } diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c index af7ddf3..cf2b79d 100644 --- a/src/cpu/amd/geode_gx2/cpubug.c +++ b/src/cpu/amd/geode_gx2/cpubug.c @@ -54,8 +54,8 @@ * for PCI writes to complete. */ msr = rdmsr(CPU_DM_CONFIG0); - msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT); - msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); + msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT); msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; wrmsr(CPU_DM_CONFIG0, msr); @@ -126,7 +126,7 @@ msr = rdmsr(MSR_GLCP+0x17); if ((msr.lo & 0xff) <= CPU_REV_2_0) { msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT)) + if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT)) return; } diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 106cb79..8cb6658 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -54,8 +54,8 @@ "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); - amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; + amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; + amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; } static void setup_ap_ramtop(void) @@ -128,7 +128,7 @@ /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1<<32) { + if (bsp_topmem2() > (uint64_t)1 << 32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if (has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index c0a69ec..5548007 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -43,7 +43,7 @@ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ movl %cr4, %eax - orl $(3<<9), %eax + orl $(3 << 9), %eax movl %eax, %cr4 /* Get the cpu_init_detected */ diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index c4eb50c..a04ec55 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -64,7 +64,7 @@ u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); - val |= (1<<17)|(1<<18); + val |= (1 << 17)|(1 << 18); pci_write_config32(dev, 0x68, val); } } diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index db779fa..e716caf 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -82,7 +82,7 @@ addrsize_no_MSR: movl $1, %eax cpuid - andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ + andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */ jz addrsize_set_high movl $0x0f, %edx @@ -208,7 +208,7 @@ /* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $(1<<12), %eax + movl $(1 << 12), %eax xorl %edx, %edx wrmsr diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 5c88dfa..8d9a4dc 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -42,8 +42,8 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define SMRR_SUPPORTED (1 << 11) +#define EMRR_SUPPORTED (1 << 12) struct smm_relocation_params { u32 smram_base; diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 1da7a4b..387fb8b 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -28,7 +28,7 @@ #include <console/console.h> #include "smi.h" -#define SMRR_SUPPORTED (1<<11) +#define SMRR_SUPPORTED (1 << 11) #define D_OPEN (1 << 6) #define D_CLS (1 << 5) diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 8ddc931..480f61a 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -190,7 +190,7 @@ /* Enable APIC */ msr = rdmsr(0x1107); - msr.lo |= 1<<24; + msr.lo |= 1 << 24; wrmsr(0x1107, msr); /* Turn on cache */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 3a6c1a0..7d6338e 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -104,12 +104,12 @@ * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1<<7) | (1<<4) ); + msr.lo |= ( (1 << 7) | (1 << 4) ); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ - msr.lo |= (1<<5); + msr.lo |= (1 << 5); wrmsr(NANO_MYSTERIOUS_MSR, msr); /* Set the maximum frequency and voltage */ @@ -117,7 +117,7 @@ /* Enable TM3 */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<3) | (1<<13) ); + msr.lo |= ( (1 << 3) | (1 << 13) ); wrmsr(MSR_IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; @@ -125,14 +125,14 @@ /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ - msr.hi |= (1<<0); /* C4e */ + msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.hi |= (1 << 0); /* C4e */ wrmsr(MSR_IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= (1<<20); + msr.lo |= (1 << 20); wrmsr(MSR_IA32_MISC_ENABLE, msr); } -- To view, visit https://review.coreboot.org/20397 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b Gerrit-Change-Number: 20397 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017