coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 30: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10695/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55009/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-Change-Number: 19759 Gerrit-PatchSet: 30 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:58:19 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake[WIP]
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19949 ) Change subject: soc/intel/apollolake: Use common gpio for apollolake[WIP] ...................................................................... Patch Set 19: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55010/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10696/ : SUCCESS -- To view, visit https://review.coreboot.org/19949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Gerrit-Change-Number: 19949 Gerrit-PatchSet: 19 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:54:15 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: device/dram/ddr2.c: Fix is_registered_ddr2
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20058 ) Change subject: device/dram/ddr2.c: Fix is_registered_ddr2 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10694/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55008/ : SUCCESS -- To view, visit https://review.coreboot.org/20058 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Gerrit-Change-Number: 20058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:38:30 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/i945/raminit.c: Refactor tRD selection
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18354 ) Change subject: nb/intel/i945/raminit.c: Refactor tRD selection ...................................................................... Patch Set 18: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10693/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55007/ : SUCCESS -- To view, visit https://review.coreboot.org/18354 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94 Gerrit-Change-Number: 18354 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:29:00 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 45: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10692/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55006/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 45 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:25:04 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 44: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55005/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10691/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 44 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Jun 2017 22:19:50 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: device/dram/ddr2.c: Fix is_registered_ddr2
by Arthur Heymans (Code Review) 06 Jun '17

06 Jun '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20058 Change subject: device/dram/ddr2.c: Fix is_registered_ddr2 ...................................................................... device/dram/ddr2.c: Fix is_registered_ddr2 Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD specifications. Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c M src/include/device/dram/ddr2.h 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/20058/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 9eb3873..4d13f94 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -40,7 +40,8 @@ int spd_dimm_is_registered_ddr2(enum spd_dimm_type type) { if ((type == SPD_DIMM_TYPE_RDIMM) - | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + || (type == SPD_DIMM_TYPE_72B_SO_RDIMM) + || (type == SPD_DIMM_TYPE_MINI_RDIMM)) return 1; return 0; diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index a752530..ea9b3ba 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -75,7 +75,7 @@ SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, SPD_DIMM_TYPE_MICRO_DIMM = 0x08, - SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_RDIMM = 0x10, SPD_DIMM_TYPE_MINI_UDIMM = 0x20, /* Masks to bits 5:0 to give the dimm type */ SPD_DIMM_TYPE_MASK = 0x3f, -- To view, visit https://review.coreboot.org/20058 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Gerrit-Change-Number: 20058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: nb/intel/x4x: Refactor setting default DQ DQS dll settings
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20057 ) Change subject: nb/intel/x4x: Refactor setting default DQ DQS dll settings ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10690/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55004/ : SUCCESS -- To view, visit https://review.coreboot.org/20057 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b7bf90085bf4ef14bbb6de852b96e04b429fca4 Gerrit-Change-Number: 20057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 21:30:57 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/x4x: Refactor setting default DQ DQS dll settings
by Arthur Heymans (Code Review) 06 Jun '17

06 Jun '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20057 Change subject: nb/intel/x4x: Refactor setting default DQ DQS dll settings ...................................................................... nb/intel/x4x: Refactor setting default DQ DQS dll settings Makes clear that this sets safe defaults, improves readability, makes it easy to restore previously trained values instead of the safe default ones. Change-Id: I6b7bf90085bf4ef14bbb6de852b96e04b429fca4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs_dll.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 94 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/20057/1 diff --git a/src/northbridge/intel/x4x/dq_dqs_dll.c b/src/northbridge/intel/x4x/dq_dqs_dll.c index 7741b6f..043f144 100644 --- a/src/northbridge/intel/x4x/dq_dqs_dll.c +++ b/src/northbridge/intel/x4x/dq_dqs_dll.c @@ -649,23 +649,6 @@ 0xdfdfdfdf, 0xbebebebe, 0x7f7f7f7f, 0xfefefefe }; -static void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting) -{ - u8 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); - u8 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); - printk(RAM_SPEW, "RT DQS: ch%d, L%d, %d.%d\n", channel, lane, - dqs_setting->tap, - dqs_setting->pi); - - saved_tap &= ~(0xf << (rank * 4)); - saved_tap |= dqs_setting->tap << (rank * 4); - MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; - - saved_pi &= ~(0x7 << (rank * 3)); - saved_pi |= dqs_setting->pi << (rank * 4); - MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; -} - static int rt_increment_dqs(struct rt_dqs_setting *setting) { if (setting->pi < 7) { diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index b5fcbd8..493867b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -462,6 +462,24 @@ setting->tap; } +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting) +{ + u8 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); + u8 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); + printk(RAM_SPEW, "RT DQS: ch%d, L%d, %d.%d\n", channel, lane, + dqs_setting->tap, + dqs_setting->pi); + + saved_tap &= ~(0xf << (rank * 4)); + saved_tap |= dqs_setting->tap << (rank * 4); + MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; + + saved_pi &= ~(0x7 << (rank * 3)); + saved_pi |= dqs_setting->pi << (rank * 4); + MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; +} + + static void program_timings(struct sysinfo *s) { u8 i; @@ -762,20 +780,6 @@ cmdset(channel, &dll_settings[CMD]); } -static void program_dq_dqs(struct sysinfo *s, u8 channel, - const struct dll_setting dll_setting[23]) -{ - int lane; - for (lane = 0; lane < 8; lane++) { - s->dqs_settings[channel][lane] = dll_setting[DQS1 + lane]; - dqsset(channel, lane, &dll_setting[DQS1 + lane]); - } - for (lane = 0; lane < 8; lane++) { - s->dq_settings[channel][lane] = dll_setting[DQ1 + lane]; - dqset(channel, lane, &dll_setting[DQ1 + lane]); - } -} - void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose) { u8 debug_level; @@ -795,7 +799,6 @@ u8 i, j, r, reg8, clk, async = 0; u16 reg16 = 0; u32 reg32 = 0; - u8 lane; const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 }; @@ -1063,55 +1066,85 @@ if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; +} - // Program DQ/DQS dll settings - reg32 = 0; - FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - switch (s->selected_timings.mem_clk) { - default: /* Should not happen */ - break; - case MEM_CLOCK_667MHz: - reg32 = 0x06db7777; - break; - case MEM_CLOCK_800MHz: - if (s->spd_type == DDR2) - reg32 = 0x00007777; - else /* DDR3 */ - reg32 = 0x06db6666; - break; - case MEM_CLOCK_1066MHz: - reg32 = 0x06db5555; - break; - case MEM_CLOCK_1333MHz: - reg32 = 0x00007777; - break; +static void select_default_dqdqs_dll_settings(struct sysinfo *s) +{ + int channel, lane; + u8 rt_pi, rt_tap; + const struct dll_setting *dll_settings; + + switch (s->selected_timings.mem_clk) { + default: /* Should not happen */ + case MEM_CLOCK_667MHz: + rt_pi = 3; + rt_tap = 7; + break; + case MEM_CLOCK_800MHz: + if (s->spd_type == DDR2) { + rt_tap = 7; + rt_pi = 0; + } else { /* DDR3 */ + rt_tap = 6; + rt_pi = 3; } + break; + case MEM_CLOCK_1066MHz: + rt_tap = 5; + rt_pi = 3; + break; + case MEM_CLOCK_1333MHz: + rt_tap = 7; + rt_pi = 0; + break; + } + + /* RT DQS: set identical settings for each rank */ + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { for (lane = 0; lane < 8; lane++) { - MCHBAR32(0x400*i + 0x540 + lane*4) = - (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) | - reg32; + s->rt_dqs_setting[channel][lane].pi = rt_pi; + s->rt_dqs_setting[channel][lane].tap = rt_tap; } } - FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - switch (s->selected_timings.mem_clk) { - default: /* Should not happen */ - break; - case MEM_CLOCK_667MHz: - program_dq_dqs(s, i, ddr2_dll_setting_667); - break; - case MEM_CLOCK_800MHz: - if (s->spd_type == DDR2) - program_dq_dqs(s, i, ddr2_dll_setting_800); - else /* DDR3 */ - program_dq_dqs(s, i, ddr3_dll_setting_800[s->nmode - 1]); - break; - case MEM_CLOCK_1066MHz: - program_dq_dqs(s, i, ddr3_dll_setting_1066[s->nmode - 1]); - break; - case MEM_CLOCK_1333MHz: - program_dq_dqs(s, i, ddr3_dll_setting_1333[s->nmode - 1]); - break; + switch (s->selected_timings.mem_clk) { + default: /* Should not happen, but makes compiler happy */ + case MEM_CLOCK_667MHz: + dll_settings = ddr2_dll_setting_667; + break; + case MEM_CLOCK_800MHz: + if (s->spd_type == DDR2) + dll_settings = ddr2_dll_setting_800; + else /* DDR3 */ + dll_settings = ddr3_dll_setting_800[s->nmode - 1]; + break; + case MEM_CLOCK_1066MHz: + dll_settings = ddr3_dll_setting_1066[s->nmode - 1]; + break; + case MEM_CLOCK_1333MHz: + dll_settings = ddr3_dll_setting_1333[s->nmode - 1]; + break; + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { + for (lane = 0; lane < 8; lane++) { + s->dqs_settings[channel][lane] = dll_settings[DQS1 + lane]; + s->dqs_settings[channel][lane] = dll_settings[DQ1 + lane]; + } + } +} + +static void program_dqdqs_settings(struct sysinfo *s) +{ + int channel, lane, rank; + /* RT DQS DLL settings */ + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { + for (lane = 0; lane < 8; lane++) { + dqsset(channel, lane, &(s->dqs_settings[channel][lane])); + dqset(channel, lane, &(s->dq_settings[channel][lane])); + for (rank = 0; rank < 4; rank++) + rt_set_dqs(channel, lane, rank, + &s->rt_dqs_setting[channel][lane]); } } } @@ -2246,6 +2279,8 @@ // Program DLL program_dll(s); + select_default_dqdqs_dll_settings(s); + program_dqdqs_settings(s); // RCOMP if (s->boot_path != BOOT_PATH_WARM_RESET) { diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 07cc71b..d78a743 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -367,6 +367,7 @@ void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); void dqset(u8 ch, u8 lane, const struct dll_setting *setting); +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting); void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose); void search_write_leveling(struct sysinfo *s); int do_write_training(struct sysinfo *s); -- To view, visit https://review.coreboot.org/20057 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b7bf90085bf4ef14bbb6de852b96e04b429fca4 Gerrit-Change-Number: 20057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: soc/baytrail: fix scope for I2C ACPI devices
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20056 ) Change subject: soc/baytrail: fix scope for I2C ACPI devices ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10688/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55002/ : SUCCESS -- To view, visit https://review.coreboot.org/20056 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692 Gerrit-Change-Number: 20056 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 21:14:53 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017