coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: soc/intel/cannonlake: Add UART initialization
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20063 ) Change subject: soc/intel/cannonlake: Add UART initialization ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10704/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55018/ : SUCCESS -- To view, visit https://review.coreboot.org/20063 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Gerrit-Change-Number: 20063 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:18:40 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: vendorcode/intel: Add initial FSP headers for Cannonlake
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20069 ) Change subject: vendorcode/intel: Add initial FSP headers for Cannonlake ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55024/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10710/ : SUCCESS -- To view, visit https://review.coreboot.org/20069 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4471c6aa40ff23179b033a873aec1887b8b4370e Gerrit-Change-Number: 20069 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:18:09 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add bootblock PCH
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20067 ) Change subject: soc/intel/cannonlake: Add bootblock PCH ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10708/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55022/ : SUCCESS -- To view, visit https://review.coreboot.org/20067 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3694e099e78c2989f7192c550cbba098e5df2032 Gerrit-Change-Number: 20067 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:17:32 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/block/cse: Add Cannonlake SoC for HECI1 device
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20064 ) Change subject: soc/intel/block/cse: Add Cannonlake SoC for HECI1 device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10706/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55020/ : SUCCESS -- To view, visit https://review.coreboot.org/20064 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida822d704b04cc4d1dfffb58003fc308bcb502d0 Gerrit-Change-Number: 20064 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:17:03 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add early CPU initialization
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20066 ) Change subject: soc/intel/cannonlake: Add early CPU initialization ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10707/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55021/ : SUCCESS -- To view, visit https://review.coreboot.org/20066 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86 Gerrit-Change-Number: 20066 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:16:43 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add utility to calculate TSC frequency
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20062 ) Change subject: soc/intel/cannonlake: Add utility to calculate TSC frequency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10703/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55017/ : SUCCESS -- To view, visit https://review.coreboot.org/20062 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76f7a102c8b13c402c5b3354f932cf75e001132e Gerrit-Change-Number: 20062 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:12:26 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add initial dummy directory
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20061 ) Change subject: soc/intel/cannonlake: Add initial dummy directory ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10701/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55015/ : SUCCESS -- To view, visit https://review.coreboot.org/20061 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Gerrit-Change-Number: 20061 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:11:21 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 31: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55016/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10702/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-Change-Number: 19759 Gerrit-PatchSet: 31 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 01:04:28 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Initial set of board files
by Andrey Petrov (Code Review) 07 Jun '17

07 Jun '17

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20075 Change subject: mainboard/intel/cannonlake_rvp: Initial set of board files ...................................................................... mainboard/intel/cannonlake_rvp: Initial set of board files Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- A src/mainboard/intel/cannonlake_rvp/Kconfig A src/mainboard/intel/cannonlake_rvp/Kconfig.name A src/mainboard/intel/cannonlake_rvp/Makefile.inc A src/mainboard/intel/cannonlake_rvp/devicetree.cb A src/mainboard/intel/cannonlake_rvp/romstage.c 5 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/20075/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig new file mode 100644 index 0000000..b2223b0 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -0,0 +1,30 @@ +if BOARD_INTEL_CANNONLAKE_RVP + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_CANNONLAKE + +config MAINBOARD_DIR + string + default "intel/cannonlake_rvp" + +config MAINBOARD_PART_NUMBER + string + default "Cannonlake RVP" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.bin" + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.bin" + +endif diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig.name b/src/mainboard/intel/cannonlake_rvp/Kconfig.name new file mode 100644 index 0000000..4935603 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_CANNONLAKE_RVP + bool "Cannonlake DDR4 RVP" diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc new file mode 100644 index 0000000..75c34dd --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -0,0 +1 @@ +#Nothing here yet diff --git a/src/mainboard/intel/cannonlake_rvp/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/devicetree.cb new file mode 100644 index 0000000..c7001a4 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/devicetree.cb @@ -0,0 +1,9 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + end +end diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c new file mode 100644 index 0000000..64752e2 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +//Nothing here yet, but file needed for build. -- To view, visit https://review.coreboot.org/20075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0 Gerrit-Change-Number: 20075 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Use common GPIO driver
by Andrey Petrov (Code Review) 07 Jun '17

07 Jun '17

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20074 Change subject: soc/intel/cannonlake: Use common GPIO driver ...................................................................... soc/intel/cannonlake: Use common GPIO driver Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig A src/soc/intel/cannonlake/gpio_private.c A src/soc/intel/cannonlake/include/soc/gpio.h A src/soc/intel/cannonlake/include/soc/gpio_defs.h A src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 5 files changed, 695 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/20074/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1e0dbdc..e4c44d9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -33,6 +33,7 @@ select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_BLOCK_GPIO config UART_DEBUG bool "Enable UART debug port." diff --git a/src/soc/intel/cannonlake/gpio_private.c b/src/soc/intel/cannonlake/gpio_private.c new file mode 100644 index 0000000..19ecd78 --- /dev/null +++ b/src/soc/intel/cannonlake/gpio_private.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 - 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> + +static const struct pad_community cnl_communities[] = { + { /* GPP A, B, G */ + .port = PID_GPIOCOM0, + .first_pad = GPP_A0, + .last_pad = GPP_G7, + .name = "GPP_ABG", + .acpi_path = "\\_SB.GPOABG" + }, { /* GPP D, F, H */ + .port = PID_GPIOCOM1, + .first_pad = GPP_D0, + .last_pad = GPP_H23, + .name = "GPP_DFH", + .acpi_path = "\\_SB.GPODFH" + }, { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPP_D0, + .last_pad = GPP_D11, + .name = "GPD", + .acpi_path = "\\_SB.GPOD" + }, { /* GPP C, E */ + .port = PID_GPIOCOM3, + .first_pad = GPP_C0, + .last_pad = GPP_E23, + .name = "GPP_CE", + .acpi_path = "\\_SB.GPOCE" + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(cnl_communities); + return cnl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + /* not implemented yet */ + return NULL; +} diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h new file mode 100644 index 0000000..befa007 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_GPIO_H_ +#define _SOC_CANNONLAKE_GPIO_H_ + +#define GPIO_NUM_PAD_CFG_REGS 4 +#include <intelblocks/gpio.h> +#include <soc/gpio_defs.h> + +#ifndef __ACPI__ +struct gpi_status { + uint32_t grp[NUM_GPI_STATUS_REGS]; +}; +#endif +#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h new file mode 100644 index 0000000..661578a --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -0,0 +1,367 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_GPIO_DEFS_H_ +#define _SOC_CANNONLAKE_GPIO_DEFS_H_ + +#include <soc/gpio_soc_defs.h> + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x1a +#define GPP_A3_IRQ 0x1b +#define GPP_A4_IRQ 0x1c +#define GPP_A5_IRQ 0x1d +#define GPP_A6_IRQ 0x1e +#define GPP_A7_IRQ 0x1f +#define GPP_A8_IRQ 0x20 +#define GPP_A9_IRQ 0x21 +#define GPP_A10_IRQ 0x22 +#define GPP_A11_IRQ 0x23 +#define GPP_A12_IRQ 0x24 +#define GPP_A13_IRQ 0x25 +#define GPP_A14_IRQ 0x26 +#define GPP_A15_IRQ 0x27 +#define GPP_A16_IRQ 0x28 +#define GPP_A17_IRQ 0x29 +#define GPP_A18_IRQ 0x2a +#define GPP_A19_IRQ 0x2b +#define GPP_A20_IRQ 0x2c +#define GPP_A21_IRQ 0x2d +#define GPP_A22_IRQ 0x2e +#define GPP_A23_IRQ 0x2f +/* Group B */ +#define GPP_B0_IRQ 0x30 +#define GPP_B1_IRQ 0x31 +#define GPP_B2_IRQ 0x32 +#define GPP_B3_IRQ 0x33 +#define GPP_B4_IRQ 0x34 +#define GPP_B5_IRQ 0x35 +#define GPP_B6_IRQ 0x36 +#define GPP_B7_IRQ 0x37 +#define GPP_B8_IRQ 0x38 +#define GPP_B9_IRQ 0x39 +#define GPP_B10_IRQ 0x3a +#define GPP_B11_IRQ 0x3b +#define GPP_B12_IRQ 0x3c +#define GPP_B13_IRQ 0x3d +#define GPP_B14_IRQ 0x3e +#define GPP_B15_IRQ 0x3f +#define GPP_B16_IRQ 0x40 +#define GPP_B17_IRQ 0x41 +#define GPP_B18_IRQ 0x42 +#define GPP_B19_IRQ 0x43 +#define GPP_B20_IRQ 0x44 +#define GPP_B21_IRQ 0x45 +#define GPP_B22_IRQ 0x46 +#define GPP_B23_IRQ 0x47 +/* Group C */ +#define GPP_C0_IRQ 0x48 +#define GPP_C1_IRQ 0x49 +#define GPP_C2_IRQ 0x4a +#define GPP_C3_IRQ 0x4b +#define GPP_C4_IRQ 0x4c +#define GPP_C5_IRQ 0x4d +#define GPP_C6_IRQ 0x4e +#define GPP_C7_IRQ 0x4f +#define GPP_C8_IRQ 0x50 +#define GPP_C9_IRQ 0x51 +#define GPP_C10_IRQ 0x52 +#define GPP_C11_IRQ 0x53 +#define GPP_C12_IRQ 0x54 +#define GPP_C13_IRQ 0x55 +#define GPP_C14_IRQ 0x56 +#define GPP_C15_IRQ 0x57 +#define GPP_C16_IRQ 0x58 +#define GPP_C17_IRQ 0x59 +#define GPP_C18_IRQ 0x5a +#define GPP_C19_IRQ 0x5b +#define GPP_C20_IRQ 0x5c +#define GPP_C21_IRQ 0x5d +#define GPP_C22_IRQ 0x5e +#define GPP_C23_IRQ 0x5f +/* Group D */ +#define GPP_D0_IRQ 0x60 +#define GPP_D1_IRQ 0x61 +#define GPP_D2_IRQ 0x62 +#define GPP_D3_IRQ 0x63 +#define GPP_D4_IRQ 0x64 +#define GPP_D5_IRQ 0x65 +#define GPP_D6_IRQ 0x66 +#define GPP_D7_IRQ 0x67 +#define GPP_D8_IRQ 0x68 +#define GPP_D9_IRQ 0x69 +#define GPP_D10_IRQ 0x6a +#define GPP_D11_IRQ 0x6b +#define GPP_D12_IRQ 0x6c +#define GPP_D13_IRQ 0x6d +#define GPP_D14_IRQ 0x6e +#define GPP_D15_IRQ 0x6f +#define GPP_D16_IRQ 0x70 +#define GPP_D17_IRQ 0x71 +#define GPP_D18_IRQ 0x72 +#define GPP_D19_IRQ 0x73 +#define GPP_D20_IRQ 0x74 +#define GPP_D21_IRQ 0x75 +#define GPP_D22_IRQ 0x76 +#define GPP_D23_IRQ 0x77 +/* Group E */ +#define GPP_E0_IRQ 0x18 +#define GPP_E1_IRQ 0x19 +#define GPP_E2_IRQ 0x1a +#define GPP_E3_IRQ 0x1b +#define GPP_E4_IRQ 0x1c +#define GPP_E5_IRQ 0x1d +#define GPP_E6_IRQ 0x1e +#define GPP_E7_IRQ 0x1f +#define GPP_E8_IRQ 0x20 +#define GPP_E9_IRQ 0x21 +#define GPP_E10_IRQ 0x22 +#define GPP_E11_IRQ 0x23 +#define GPP_E12_IRQ 0x24 +#define GPP_E13_IRQ 0x25 +#define GPP_E14_IRQ 0x26 +#define GPP_E15_IRQ 0x27 +#define GPP_E16_IRQ 0x28 +#define GPP_E17_IRQ 0x29 +#define GPP_E18_IRQ 0x2a +#define GPP_E19_IRQ 0x2b +#define GPP_E20_IRQ 0x2c +#define GPP_E21_IRQ 0x2d +#define GPP_E22_IRQ 0x2e +#define GPP_E23_IRQ 0x2f +/* Group F */ +#define GPP_F0_IRQ 0x0 +#define GPP_F1_IRQ 0x30 +#define GPP_F2_IRQ 0x31 +#define GPP_F3_IRQ 0x32 +#define GPP_F4_IRQ 0x33 +#define GPP_F5_IRQ 0x34 +#define GPP_F6_IRQ 0x35 +#define GPP_F7_IRQ 0x36 +#define GPP_F8_IRQ 0x37 +#define GPP_F9_IRQ 0x38 +#define GPP_F10_IRQ 0x39 +#define GPP_F11_IRQ 0x3a +#define GPP_F12_IRQ 0x3b +#define GPP_F13_IRQ 0x3c +#define GPP_F14_IRQ 0x3d +#define GPP_F15_IRQ 0x3e +#define GPP_F16_IRQ 0x3f +#define GPP_F17_IRQ 0x40 +#define GPP_F18_IRQ 0x41 +#define GPP_F19_IRQ 0x42 +#define GPP_F20_IRQ 0x43 +#define GPP_F21_IRQ 0x44 +#define GPP_F22_IRQ 0x45 +#define GPP_F23_IRQ 0x46 +/* Group G */ +#define GPP_G0_IRQ 0x6c +#define GPP_G1_IRQ 0x6d +#define GPP_G2_IRQ 0x6e +#define GPP_G3_IRQ 0x6f +#define GPP_G4_IRQ 0x70 +#define GPP_G5_IRQ 0x71 +#define GPP_G6_IRQ 0x72 +#define GPP_G7_IRQ 0x73 +/* Group GPD */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6a +#define GPD11_IRQ 0x6b +/* Group H */ +#define GPP_H0_IRQ 0x47 +#define GPP_H1_IRQ 0x48 +#define GPP_H2_IRQ 0x49 +#define GPP_H3_IRQ 0x4a +#define GPP_H4_IRQ 0x4b +#define GPP_H5_IRQ 0x4c +#define GPP_H6_IRQ 0x4d +#define GPP_H7_IRQ 0x4e +#define GPP_H8_IRQ 0x4f +#define GPP_H9_IRQ 0x50 +#define GPP_H10_IRQ 0x51 +#define GPP_H11_IRQ 0x52 +#define GPP_H12_IRQ 0x53 +#define GPP_H13_IRQ 0x54 +#define GPP_H14_IRQ 0x55 +#define GPP_H15_IRQ 0x56 +#define GPP_H16_IRQ 0x57 +#define GPP_H17_IRQ 0x58 +#define GPP_H18_IRQ 0x59 +#define GPP_H19_IRQ 0x5a +#define GPP_H20_IRQ 0x5b +#define GPP_H21_IRQ 0x5c +#define GPP_H22_IRQ 0x5d +#define GPP_H23_IRQ 0x5e + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPIO_DRIVER_IRQ_ROUTE_MASK 8 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ14 0 +#define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define PAD_OWN_REG_OFFSET 0x20 +#define PAD_OWN_PADS_PER 8 +#define PAD_OWN_WIDTH_PER 4 +#define PAD_OWN_MASK 0x03 +#define PAD_OWN_HOST 0x00 +#define PAD_OWN_ME 0x01 +#define PAD_OWN_ISH 0x02 +#define HOSTSW_OWN_REG_0 0xb0 +/* DW0 */ + /* PADRSTCFG - when to reset the pad config */ +#define PADRSTCFG_SHIFT 30 +#define PADRSTCFG_MASK 0x3 +#define PADRSTCFG_DSW_PWROK 0 +#define PADRSTCFG_DEEP 1 +#define PADRSTCFG_PLTRST 2 +#define PADRSTCFG_RSMRST 3 + /* RXPADSTSEL - raw signal or internal state */ +#define RXPADSTSEL_SHIFT 29 +#define RXPADSTSEL_MASK 0x1 +#define RXPADSTSEL_RAW 0 +#define RXPADSTSEL_INTERNAL 1 + /* RXRAW1 - drive 1 instead instead of pad value */ +#define RXRAW1_SHIFT 28 +#define RXRAW1_MASK 0x1 +#define RXRAW1_NO 0 +#define RXRAW1_YES 1 + /* RXEVCFG - Interrupt and wake types */ +#define RXEVCFG_SHIFT 25 +#define RXEVCFG_MASK 0x3 +#define RXEVCFG_LEVEL 0 +#define RXEVCFG_EDGE 1 /* RXINV =0 for rising edge; 1 for failing edge */ +#define RXEVCFG_DISABLE 2 +#define RXEVCFG_EITHEREDGE 3 + /* PREGFRXSEL - use filtering on Rx pad */ +#define PREGFRXSEL_SHIFT 24 +#define PREGFRXSEL_MASK 0x1 +#define PREGFRXSEL_NO 0 +#define PREGFRXSEL_YES 1 + /* RXINV - invert signal to SMI, SCI, NMI, or IRQ routing. */ +#define RXINV_SHIFT 23 +#define RXINV_MASK 0x1 +#define RXINV_NO 0 +#define RXINV_YES 1 + /* GPIROUTIOXAPIC - route to io-xapic or not */ +#define GPIROUTIOXAPIC_SHIFT 20 +#define GPIROUTIOXAPIC_MASK 0x1 +#define GPIROUTIOXAPIC_NO 0 +#define GPIROUTIOXAPIC_YES 1 + /* GPIROUTSCI - route to SCI */ +#define GPIROUTSCI_SHIFT 19 +#define GPIROUTSCI_MASK 0x1 +#define GPIROUTSCI_NO 0 +#define GPIROUTSCI_YES 1 + /* GPIROUTSMI - route to SMI */ +#define GPIROUTSMI_SHIFT 18 +#define GPIROUTSMI_MASK 0x1 +#define GPIROUTSMI_NO 0 +#define GPIROUTSMI_YES 1 + /* GPIROUTNMI - route to NMI */ +#define GPIROUTNMI_SHIFT 17 +#define GPIROUTNMI_MASK 0x1 +#define GPIROUTNMI_NO 0 +#define GPIROUTNMI_YES 1 + /* PMODE - mode of pad */ +#define PMODE_SHIFT 10 +#define PMODE_MASK 0x3 +#define PMODE_GPIO 0 +#define PMODE_NF1 1 +#define PMODE_NF2 2 +#define PMODE_NF3 3 + /* GPIORXDIS - Disable Rx */ +#define GPIORXDIS_SHIFT 9 +#define GPIORXDIS_MASK 0x1 +#define GPIORXDIS_NO 0 +#define GPIORXDIS_YES 1 + /* GPIOTXDIS - Disable Tx */ +#define GPIOTXDIS_SHIFT 8 +#define GPIOTXDIS_MASK 0x1 +#define GPIOTXDIS_NO 0 +#define GPIOTXDIS_YES 1 + /* GPIORXSTATE - Internal state after glitch filter */ +#define GPIORXSTATE_SHIFT 1 +#define GPIORXSTATE_MASK 0x1 + /* GPIOTXSTATE - Drive value onto pad */ +#define GPIOTXSTATE_SHIFT 0 +#define GPIOTXSTATE_MASK 0x1 +/* DW1 */ + /* TERM - termination control */ +#define PAD_TERM_SHIFT 10 +#define PAD_TERM_MASK 0xf +#define PAD_TERM_NONE 0 +#define PAD_TERM_5K_PD 2 +#define PAD_TERM_20K_PD 4 +#define PAD_TERM_1K_PU 9 +#define PAD_TERM_2K_PU 11 +#define PAD_TERM_5K_PU 10 +#define PAD_TERM_20K_PU 12 +#define PAD_TERM_667_PU 13 +#define PAD_TERM_NATIVE 15 + /* TOL - voltage tolerance */ +#define PAD_TOL_SHIFT 25 +#define PAD_TOL_MASK 0x1 +#define PAD_TOL_3V3 0 /* 3.3V default */ +#define PAD_TOL_1V8 1 /* 1.8V tolerant */ +/* DW2 */ + /* DEBONDUR - Debounce duration */ +#define DEBONDUR_SHIFT 1 +#define DEBONDUR_MASK 0xf +#define DEBONDUR_NONE 0 +#define DEBONDUR_DEBOUNCE_3 3 +#define DEBONDUR_DEBOUNCE_4 4 +#define DEBONDUR_DEBOUNCE_5 5 +#define DEBONDUR_DEBOUNCE_6 6 +#define DEBONDUR_DEBOUNCE_7 7 +#define DEBONDUR_DEBOUNCE_8 8 +#define DEBONDUR_DEBOUNCE_9 9 +#define DEBONDUR_DEBOUNCE_10 10 +#define DEBONDUR_DEBOUNCE_11 11 +#define DEBONDUR_DEBOUNCE_12 12 +#define DEBONDUR_DEBOUNCE_13 13 +#define DEBONDUR_DEBOUNCE_14 14 +#define DEBONDUR_DEBOUNCE_15 15 + /* DEBONEN - Debounce enable */ +#define DEBON_SHIFT 0 +#define DEBON_MASK 1 +#define DEBON_DISABLE 0 +#define DEBON_ENABLE 1 + +#define PAD_CFG_BASE 0x600 + +#define GPI_SMI_STS_0 0x100 +#define GPI_SMI_EN_0 0x120 +#define GPI_SMI_STS_OFFSET(group) (GPI_SMI_STS_0 + ((group) * 4)) +#define GPI_SMI_EN_OFFSET(group) (GPI_SMI_EN_0 + ((group) * 4)) + +#define NUM_GPI_STATUS_REGS 8 + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..afa1c22 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_ +#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_H_ + +/* + * There are 9 GPIO groups. GPP_A -> GPP_H and GPD. GPD is the special case + * where that group is not so generic. So most of the fixed numbers and macros + * are based on the GPP groups. The GPIO groups are accessed through register + * blocks called communities. + */ +#define GPP_A 0 +#define GPP_B 1 +#define GPP_G 2 +#define GPP_D 3 +#define GPP_F 4 +#define GPP_H 5 +#define GPP_C 6 +#define GPP_E 7 +#define GPD 8 +#define GPIO_NUM_GROUPS 9 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group G */ +#define GPP_G0 48 +#define GPP_G1 49 +#define GPP_G2 50 +#define GPP_G3 51 +#define GPP_G4 52 +#define GPP_G5 53 +#define GPP_G6 54 +#define GPP_G7 55 +/* Group D */ +#define GPP_D0 56 +#define GPP_D1 57 +#define GPP_D2 58 +#define GPP_D3 59 +#define GPP_D4 60 +#define GPP_D5 61 +#define GPP_D6 62 +#define GPP_D7 63 +#define GPP_D8 64 +#define GPP_D9 65 +#define GPP_D10 66 +#define GPP_D11 67 +#define GPP_D12 68 +#define GPP_D13 69 +#define GPP_D14 70 +#define GPP_D15 71 +#define GPP_D16 72 +#define GPP_D17 73 +#define GPP_D18 74 +#define GPP_D19 75 +#define GPP_D20 76 +#define GPP_D21 77 +#define GPP_D22 78 +#define GPP_D23 79 +/* Group F */ +#define GPP_F0 80 +#define GPP_F1 81 +#define GPP_F2 82 +#define GPP_F3 83 +#define GPP_F4 84 +#define GPP_F5 85 +#define GPP_F6 86 +#define GPP_F7 87 +#define GPP_F8 88 +#define GPP_F9 89 +#define GPP_F10 90 +#define GPP_F11 91 +#define GPP_F12 92 +#define GPP_F13 93 +#define GPP_F14 94 +#define GPP_F15 95 +#define GPP_F16 96 +#define GPP_F17 97 +#define GPP_F18 98 +#define GPP_F19 99 +#define GPP_F20 100 +#define GPP_F21 101 +#define GPP_F22 102 +#define GPP_F23 103 +/* Group H */ +#define GPP_H0 104 +#define GPP_H1 105 +#define GPP_H2 106 +#define GPP_H3 107 +#define GPP_H4 108 +#define GPP_H5 109 +#define GPP_H6 110 +#define GPP_H7 111 +#define GPP_H8 112 +#define GPP_H9 113 +#define GPP_H10 114 +#define GPP_H11 115 +#define GPP_H12 116 +#define GPP_H13 117 +#define GPP_H14 118 +#define GPP_H15 119 +#define GPP_H16 120 +#define GPP_H17 121 +#define GPP_H18 122 +#define GPP_H19 123 +#define GPP_H20 124 +#define GPP_H21 125 +#define GPP_H22 126 +#define GPP_H23 127 +/* Group C */ +#define GPP_C0 128 +#define GPP_C1 129 +#define GPP_C2 130 +#define GPP_C3 131 +#define GPP_C4 132 +#define GPP_C5 133 +#define GPP_C6 134 +#define GPP_C7 135 +#define GPP_C8 136 +#define GPP_C9 137 +#define GPP_C10 138 +#define GPP_C11 139 +#define GPP_C12 140 +#define GPP_C13 141 +#define GPP_C14 142 +#define GPP_C15 143 +#define GPP_C16 144 +#define GPP_C17 145 +#define GPP_C18 146 +#define GPP_C19 147 +#define GPP_C20 148 +#define GPP_C21 149 +#define GPP_C22 150 +#define GPP_C23 151 +/* Group E */ +#define GPP_E0 152 +#define GPP_E1 153 +#define GPP_E2 154 +#define GPP_E3 155 +#define GPP_E4 156 +#define GPP_E5 157 +#define GPP_E6 158 +#define GPP_E7 159 +#define GPP_E8 160 +#define GPP_E9 161 +#define GPP_E10 162 +#define GPP_E11 163 +#define GPP_E12 164 +#define GPP_E13 165 +#define GPP_E14 166 +#define GPP_E15 167 +#define GPP_E16 168 +#define GPP_E17 169 +#define GPP_E18 170 +#define GPP_E19 171 +#define GPP_E20 172 +#define GPP_E21 173 +#define GPP_E22 174 +#define GPP_E23 175 +/* Group GPD */ +#define GPD0 176 +#define GPD1 177 +#define GPD2 178 +#define GPD3 179 +#define GPD4 180 +#define GPD5 181 +#define GPD6 182 +#define GPD7 183 +#define GPD8 184 +#define GPD9 185 +#define GPD10 186 +#define GPD11 187 + +#endif -- To view, visit https://review.coreboot.org/20074 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5 Gerrit-Change-Number: 20074 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017