coreboot-gerrit June 2017

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Change in coreboot[master]: soc/intel/cannonlake: Add UART initialization
by Andrey Petrov (Code Review) 07 Jun '17

07 Jun '17

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20063 Change subject: soc/intel/cannonlake: Add UART initialization ...................................................................... soc/intel/cannonlake: Add UART initialization Cannonlake has built-in UART driver as part of LPSS block. However port mapped decoders are in use as well. Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- A src/soc/intel/cannonlake/uart.c 1 file changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/20063/1 diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c new file mode 100644 index 0000000..8e33d77 --- /dev/null +++ b/src/soc/intel/cannonlake/uart.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <device/pci_def.h> +#include <intelblocks/gpio.h> +#include <intelblocks/lpss.h> +#include <intelblocks/pcr.h> +#include <intelblocks/uart.h> +#include <soc/bootblock.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/iomap.h> + +/* Serial IO UART controller legacy mode */ +#define PCR_SERIAL_IO_GPPRVRW7 0x618 +#define PCR_SIO_PCH_LEGACY_UART0 (1 << 0) +#define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) +#define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) + +/* Clock divider parameters for 115200 baud rate */ +#define CLK_M_VAL 0x30 +#define CLK_N_VAL 0xc35 + +/* UART2 pad configuration. Support RXD and TXD for now. */ +static const struct pad_config uart2_pads[] = { +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +void pch_uart_init(void) +{ + uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + + uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL); + + /* Put UART2 in byte access mode for 16550 compatibility */ + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART2); + gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +uintptr_t uart_platform_base(int idx) +{ + /* Same base address for all debug port usage. In reality UART2 + * is currently only supported. */ + return UART_DEBUG_BASE_ADDRESS; +} -- To view, visit https://review.coreboot.org/20063 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195 Gerrit-Change-Number: 20063 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add utility to calculate TSC frequency
by Andrey Petrov (Code Review) 07 Jun '17

07 Jun '17

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/20062 Change subject: soc/intel/cannonlake: Add utility to calculate TSC frequency ...................................................................... soc/intel/cannonlake: Add utility to calculate TSC frequency Change-Id: I76f7a102c8b13c402c5b3354f932cf75e001132e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- A src/soc/intel/cannonlake/tsc_freq.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/20062/1 diff --git a/src/soc/intel/cannonlake/tsc_freq.c b/src/soc/intel/cannonlake/tsc_freq.c new file mode 100644 index 0000000..f8f91e6 --- /dev/null +++ b/src/soc/intel/cannonlake/tsc_freq.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> +#include <soc/msr.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); +} -- To view, visit https://review.coreboot.org/20062 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76f7a102c8b13c402c5b3354f932cf75e001132e Gerrit-Change-Number: 20062 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add initial dummy directory
by Andrey Petrov (Code Review) 07 Jun '17

07 Jun '17

Hello Lijian Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/20061 to review the following change. Change subject: soc/intel/cannonlake: Add initial dummy directory ...................................................................... soc/intel/cannonlake: Add initial dummy directory Add CannonLake SoC broilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- A src/soc/intel/cannonlake/Kconfig A src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/cbmem.c 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/20061/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig new file mode 100644 index 0000000..1e0dbdc --- /dev/null +++ b/src/soc/intel/cannonlake/Kconfig @@ -0,0 +1,69 @@ +config SOC_INTEL_CANNONLAKE + bool + help + Intel Cannonlake support + +if SOC_INTEL_CANNONLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select HAVE_MONOTONIC_TIMER + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select REG_SCRIPT + select C_ENVIRONMENT_BOOTBLOCK + select HAVE_HARD_RESET + select HAVE_INTEL_FIRMWARE + select INTEL_CAR_NEM_ENHANCED + select PLATFORM_USES_FSP2_0 + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CAR + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_BLOCK_LPSS + select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_CSE + +config UART_DEBUG + bool "Enable UART debug port." + default y + select CONSOLE_SERIAL + select BOOTBLOCK_CONSOLE + select DRIVERS_UART + select DRIVERS_UART_8250IO + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x40000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc new file mode 100644 index 0000000..4651a23 --- /dev/null +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) + +romstage-y += cbmem.c + +ramstage-y += cbmem.c + +endif diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c new file mode 100644 index 0000000..21a1d03 --- /dev/null +++ b/src/soc/intel/cannonlake/cbmem.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *) NULL; +} -- To view, visit https://review.coreboot.org/20061 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Gerrit-Change-Number: 20061 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/braswell: fix ACPI table by recollecting TOLM
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20060 ) Change subject: soc/braswell: fix ACPI table by recollecting TOLM ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10700/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55014/ : SUCCESS -- To view, visit https://review.coreboot.org/20060 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0 Gerrit-Change-Number: 20060 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Harry Pan <harry.pan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 00:36:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/braswell: fix ACPI table by recollecting TOLM
by Matt DeVillier (Code Review) 07 Jun '17

07 Jun '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20060 Change subject: soc/braswell: fix ACPI table by recollecting TOLM ...................................................................... soc/braswell: fix ACPI table by recollecting TOLM cherry-pick from Chromium, commit 8fbe1e7 On Braswell and Baytrail devices, by userland 'perf top', observed demanding clocks on __vdso_clock_gettime() since chromeos_3.18 kernel; besides, evaluated massive calling of clock_gettime() cost, up to 700 ns in average. It turns out that Linux kernel of map_vdso() first call of remap_pfn_range() does not fall into reserve_pfn_range() due to size parameter, instead it relies on lookup_memtype() and potentially be failed to be identified as eligible RAM resource because the function of pat_pagerange_is_ram() actually walks through root's sibling. Meanwhile, on current BSW (and BYT) firmware implementation makes System RAM resources located on child leaf, combining all of these factors makes the kernel treat the vvar page of vdso as a uncached-minus one leading slow access in result. This patch recollects TOLM accessing; as Aaron recalled some core_msr_script turns off access to TOLM register, he suggests to store tolm to avoid getting back a zero while setting acpi nvs space. Original-Change-Id: Iad4ffa542b22073cb087100a95169e2d2a52efcd Original-Signed-off-by: Harry Pan <harry.pan(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/368585 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/20060/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 404a8f1..dc72a46 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -29,6 +29,7 @@ #include <soc/ramstage.h> #include <soc/smm.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <stddef.h> /* * Host Memory Map: @@ -70,7 +71,14 @@ uint32_t nc_read_top_of_low_memory(void) { - return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); + MAYBE_STATIC uint32_t tolm = 0; + + if (tolm) + return tolm; + + tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); + + return tolm; } static void nc_read_resources(device_t dev) -- To view, visit https://review.coreboot.org/20060 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idc9765ec5c0920dc98baeb9267a89bec5cadd5a0 Gerrit-Change-Number: 20060 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Harry Pan <harry.pan(a)intel.com>

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Change in coreboot[master]: vendorcode/intel: Update FSP header files as per v48_20
by Ravishankar Sarawadi (Code Review) 06 Jun '17

06 Jun '17

Ravishankar Sarawadi has abandoned this change. ( https://review.coreboot.org/20059 ) Change subject: vendorcode/intel: Update FSP header files as per v48_20 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/20059 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I62b48bc1432e8d24baa1da4918a5b4b73b14597a Gerrit-Change-Number: 20059 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: vendorcode/intel: Update FSP header files as per v48_20
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20059 ) Change subject: vendorcode/intel: Update FSP header files as per v48_20 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10699/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55013/ : SUCCESS -- To view, visit https://review.coreboot.org/20059 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I62b48bc1432e8d24baa1da4918a5b4b73b14597a Gerrit-Change-Number: 20059 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 23:48:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: vendorcode/intel: Update FSP header files as per v48_20
by Ravishankar Sarawadi (Code Review) 06 Jun '17

06 Jun '17

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/20059 to review the following change. Change subject: vendorcode/intel: Update FSP header files as per v48_20 ...................................................................... vendorcode/intel: Update FSP header files as per v48_20 Also add VariableNvsBufferPtr UPD. Change-Id: I62b48bc1432e8d24baa1da4918a5b4b73b14597a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 3 files changed, 92 insertions(+), 155 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/20059/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h index d1bb1fc..354dd8a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h @@ -37,11 +37,11 @@ #pragma pack(push, 1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554B4C47 /* 'GLKUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B4C47 /* 'GLKUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554B4C47 /* 'GLKUPD_S' */ #pragma pack(pop) diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h index 2619171..6478f35 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -35,7 +35,7 @@ #include <FspUpd.h> -#pragma pack(push, 1) +#pragma pack(1) #define MAX_CHANNELS_NUM 4 @@ -157,25 +157,21 @@ UINT8 Package; /** Offset 0x004E - Profile - Profile list. 0x19(Default). - 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, - 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, - 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, - 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, - 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, - 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, - 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, - 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, - 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, - 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, - 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, - 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 + Profile list. 0x15(Default). + 0x01:LPDDR3_1333_10_12_12, 0x02:LPDDR3_1600_12_15_15, 0x03:LPDDR3_1866_14_17_17, + 0x04:LPDDR4_1600_14_15_15, 0x05:LPDDR4_1866_20_17_17, 0x06:LPDDR4_2133_20_20_20, + 0x07:LPDDR4_2400_24_22_22, 0x08:LPDDR4_2666_24_24_24, 0x09:LPDDR4_3200_28_29_29, + 0x0A:DDR4_1600_10_10_10, 0x0B:DDR4_1600_11_11_11, 0x0C:DDR4_1600_12_12_12, 0x0D:DDR4_1866_12_12_12, + 0x0E:DDR4_1866_13_13_13, 0x0F:DDR4_1866_14_14_14, 0x10:DDR4_2133_14_14_14, 0x11:DDR4_2133_15_15_15, + 0x12:DDR4_2133_16_16_16, 0x13:DDR4_2400_15_15_15, 0x14:DDR4_2400_16_16_16, 0x15:DDR4_2400_17_17_17, + 0x16:DDR4_2400_18_18_18, 0x17:DDR4_2666_17_17_17, 0x18:DDR4_2666_18_18_18, 0x19:DDR4_2666_19_19_19, + 0x1A:DDR4_2666_20_20_20 **/ UINT8 Profile; /** Offset 0x004F - MemoryDown Memory Down. 0x0(Default). - 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L/4 only) ACRD, 0x3:1x32 LPDDR4 **/ UINT8 MemoryDown; @@ -302,7 +298,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch0_DeviceWidth; @@ -314,7 +310,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch0_DramDensity; @@ -383,7 +379,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch1_DeviceWidth; @@ -395,7 +391,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch1_DramDensity; @@ -453,7 +449,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch2_DeviceWidth; @@ -465,7 +461,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch2_DramDensity; @@ -523,7 +519,7 @@ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4 and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16 device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64 - 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 + 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64 **/ UINT8 Ch3_DeviceWidth; @@ -535,7 +531,7 @@ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration, a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 - 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved - 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb + 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb **/ UINT8 Ch3_DramDensity; @@ -820,36 +816,26 @@ **/ UINT8 EnableS3Heci2; -/** Offset 0x0152 +/** Offset 0x0152 - PCI Express Root Port + Control the PCI Express Root Port . 0:Disable, 1:Enable, 2:Auto(Default). **/ - UINT8 ReservedFspmUpd[3]; + UINT8 PcieRootPortEn[6]; + +/** Offset 0x0158 - PCIE SLOT Power Enable Assert Time - PFET. + ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will + wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer + who designed the board PCIE slot Power automatically enabled, can pass value of + zero here. +**/ + UINT64 StartTimerTickerOfPfetAssert; + +/** Offset 0x0160 **/ + VOID* VariableNvsBufferPtr; + +/** Offset 0x0164 +**/ + UINT8 ReservedFspmUpd[4]; } FSP_M_CONFIG; - -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0155 -**/ - UINT32 Signature; - -/** Offset 0x0159 -**/ - UINT8 ReservedFspmTestUpd[28]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0175 -**/ - UINT32 Signature; - -/** Offset 0x0179 -**/ - UINT8 ReservedFspmRestrictedUpd[124]; -} FSP_M_RESTRICTED_CONFIG; /** Fsp M UPD Configuration **/ @@ -867,23 +853,16 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0155 +/** Offset 0x0168 **/ - FSP_M_TEST_CONFIG FspmTestConfig; + UINT8 UnusedUpdSpace1[150]; -/** Offset 0x0175 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01F5 -**/ - UINT8 UnusedUpdSpace1[14]; - -/** Offset 0x0203 +/** Offset 0x01FE **/ UINT16 UpdTerminator; } FSPM_UPD; -#pragma pack(pop) +#pragma pack() #endif + diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index 081fb94..7f0bbe6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -35,7 +35,7 @@ #include <FspUpd.h> -#pragma pack(push, 1) +#pragma pack(1) /** Fsp S Configuration @@ -1522,161 +1522,122 @@ **/ UINT64 SgxEpoch1; -/** Offset 0x0343 - Selective enable SGX - Selective enable SGX. 0xFFFF(Default). -**/ - UINT16 SelectiveEnableSgx; - -/** Offset 0x0345 - SGX debug mode - Select SGX mode. 0:Disable(default), 1:Enable - 0:Disable(default), 1:Enable -**/ - UINT8 SgxDebugMode; - -/** Offset 0x0346 - MicrocodePatchAddress +/** Offset 0x0343 - MicrocodePatchAddress MicrocodePatchAddress. 0x0(Default). **/ UINT64 MicrocodePatchAddress; -/** Offset 0x034E - SGX Launch Control Policy Mode - Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default) - 0:Intel - Default, 1:Per-boot Select mode(default) -**/ - UINT8 LcpMode; - -/** Offset 0x034F - LE KeyHash0 - LE KeyHash0. 0x0(Default). -**/ - UINT64 SgxLeKeyHash0; - -/** Offset 0x0357 - LE KeyHash1 - LE KeyHash1. 0x0(Default). -**/ - UINT64 SgxLeKeyHash1; - -/** Offset 0x035F - LE KeyHash2 - LE KeyHash2. 0x0(Default). -**/ - UINT64 SgxLeKeyHash2; - -/** Offset 0x0367 - LE KeyHash3 - LE KeyHash3. 0x0(Default). -**/ - UINT64 SgxLeKeyHash3; - -/** Offset 0x036F - CNVi Mode +/** Offset 0x034B - CNVi Mode Selects CNVi Mode. 0:Disable, 1:Auto(Default). $EN_DIS **/ UINT8 CnviMode; -/** Offset 0x0370 - BT Interface +/** Offset 0x034C - BT Interface CNVi BT interface. 0:UART, 1:USB(Default). $EN_DIS **/ UINT8 CnviBtInterface; -/** Offset 0x0371 - Disable Sx Wake +/** Offset 0x034D - Disable Sx Wake Enables/Disables wake from Sx . 0:No(Default), 1:Yes. $EN_DIS **/ - UINT8 PowerRailMerge; + UINT8 DisableSxWake; -/** Offset 0x0372 - ModifyCrfGpios +/** Offset 0x034E - ModifyCrfGpios Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration of GNSS and BtOnUart gpios will/will not be done based on this policy $EN_DIS **/ UINT8 ModifyCrfGpios; -/** Offset 0x0373 - dGPU Hold Reset +/** Offset 0x034F - dGPU Hold Reset dGPU Hold Reset GPIO information from GPIO community, Pin and Active **/ UINT8 HgDgpuHoldRst[8]; -/** Offset 0x037B - dGPU Power Enable +/** Offset 0x0357 - dGPU Power Enable dGPU power enable GPIO information from GPIO community, Pin and Active **/ UINT8 HgDgpuPwrEnable[8]; -/** Offset 0x0383 - dGPU Delay after power enable +/** Offset 0x035F - dGPU Delay after power enable Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum , 300 : Default 0 : Minimum , 1000 : Maximum , 300 : Default **/ UINT16 HgDelayAfterPwrEn; -/** Offset 0x0385 - dGPU Delay after hold reset +/** Offset 0x0361 - dGPU Delay after hold reset Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum , 100 : Default 0 : Minimum , 1000 : Maximum , 100 : Default **/ UINT16 HgDelayAfterHoldReset; -/** Offset 0x0387 - HG Enable +/** Offset 0x0363 - HG Enable Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable 0x1:Enabled, 0x0:Disabled **/ UINT8 HgEnabled; -/** Offset 0x0388 - PAVP ASMF +/** Offset 0x0364 - PAVP ASMF Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 PavpAsmf; -/** Offset 0x0389 - CpuS3ResumeMtrrDataSize +/** Offset 0x0365 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data. **/ UINT16 CpuS3ResumeMtrrDataSize; -/** Offset 0x038B - CpuS3ResumeMtrrData +/** Offset 0x0367 - CpuS3ResumeMtrrData Pointer CPU S3 Resume MTRR Data **/ UINT32 CpuS3ResumeMtrrData; -/** Offset 0x038F - PAVP Auto TearDown Grace Period Enable +/** Offset 0x036B - PAVP Auto TearDown Grace Period Enable Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 AutoTearDownGracePeriod; -/** Offset 0x0390 - SeC EndOfPost EnableDisable +/** Offset 0x036C - SeC EndOfPost EnableDisable Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default). $EN_DIS **/ UINT8 EndOfPostEnabled; -/** Offset 0x0391 +/** Offset 0x036D - EnableDigitalThermalSensor EnableDisable + Enable/Disable EnableDigitalThermalSensor 0:Disable(Default), 1:Enable. + $EN_DIS +**/ + UINT8 EnableDigitalThermalSensor; + +/** Offset 0x036E - PNP Mode + Select PNP Mode. 0:Disable,1:Power,2:Performance,3:Power&Performance + 0:Disable,1:Power,2:Performance,3:Power&Performance(default) +**/ + UINT8 PnpSettings; + +/** Offset 0x036F - OsBoot EnableDisable + Select OsBoot. 1:EMMC boot, 0:HardDisk boot + 1:EMMC boot, 1:HardDisk boot +**/ + UINT8 OsBoot; + +/** Offset 0x0370 - AP threads Idle Manner + AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP + $EN_DIS +**/ + UINT8 ApIdleManner; + +/** Offset 0x0371 **/ UINT8 ReservedFspsUpd[3]; } FSP_S_CONFIG; - -/** Fsp S Test Configuration -**/ -typedef struct { - -/** Offset 0x0394 -**/ - UINT32 Signature; - -/** Offset 0x0398 -**/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; - -/** Fsp S Restricted Configuration -**/ -typedef struct { - -/** Offset 0x03A4 -**/ - UINT32 Signature; - -/** Offset 0x03A8 -**/ - UINT8 ReservedFspsRestrictedUpd[2]; -} FSP_S_RESTRICTED_CONFIG; /** Fsp S UPD Configuration **/ @@ -1690,19 +1651,16 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0394 +/** Offset 0x0374 **/ - FSP_S_TEST_CONFIG FspsTestConfig; + UINT8 UnusedUpdSpace7[58]; -/** Offset 0x03A4 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x03AA +/** Offset 0x03AE **/ UINT16 UpdTerminator; } FSPS_UPD; -#pragma pack(pop) +#pragma pack() #endif + -- To view, visit https://review.coreboot.org/20059 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62b48bc1432e8d24baa1da4918a5b4b73b14597a Gerrit-Change-Number: 20059 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: mainboard/intel/glkrvp: Add support for GLKRVP
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19604 ) Change subject: mainboard/intel/glkrvp: Add support for GLKRVP ...................................................................... Patch Set 49: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55012/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10698/ : SUCCESS -- To view, visit https://review.coreboot.org/19604 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef Gerrit-Change-Number: 19604 Gerrit-PatchSet: 49 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 23:16:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Bring in delta for GLK SOC
by build bot (Jenkins) (Code Review) 06 Jun '17

06 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19603 ) Change subject: soc/intel/apollolake: Bring in delta for GLK SOC ...................................................................... Patch Set 71: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10697/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55011/ : SUCCESS -- To view, visit https://review.coreboot.org/19603 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Gerrit-Change-Number: 19603 Gerrit-PatchSet: 71 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Jun 2017 23:09:15 +0000 Gerrit-HasComments: No

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