coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Use common systemagent code
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19796 ) Change subject: soc/intel/skylake: Use common systemagent code ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10733/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55049/ : SUCCESS -- To view, visit https://review.coreboot.org/19796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Gerrit-Change-Number: 19796 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:36:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19668 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 13: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10735/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55051/ : FAILURE -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-Change-Number: 19668 Gerrit-PatchSet: 13 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:25:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Add ports and endpoints configuration ...
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20053 ) Change subject: mb/google/poppy:[WIP] Add ports and endpoints configuration for sensor and CIO2 devices ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10731/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55047/ : SUCCESS -- To view, visit https://review.coreboot.org/20053 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Gerrit-Change-Number: 20053 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:23:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Add MIPI camera support.
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19621 ) Change subject: mb/google/poppy:[WIP] Add MIPI camera support. ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10730/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55046/ : SUCCESS -- To view, visit https://review.coreboot.org/19621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Gerrit-Change-Number: 19621 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:22:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Remove MIPI camera support from device...
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19619 ) Change subject: mb/google/poppy:[WIP] Remove MIPI camera support from devicetree.cb ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10729/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55045/ : SUCCESS -- To view, visit https://review.coreboot.org/19619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Gerrit-Change-Number: 19619 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:20:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Add camera devices power sequencing th...
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20054 ) Change subject: mb/google/poppy:[WIP] Add camera devices power sequencing through ACPI power resources ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10732/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55048/ : FAILURE -- To view, visit https://review.coreboot.org/20054 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Gerrit-Change-Number: 20054 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 06:16:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Add camera devices power sequencing th...
by V Sowmya (Code Review) 07 Jun '17

07 Jun '17

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/20054 to review the following change. Change subject: mb/google/poppy:[WIP] Add camera devices power sequencing through ACPI power resources ...................................................................... mb/google/poppy:[WIP] Add camera devices power sequencing through ACPI power resources This patch controls the camera devices power through ACPI power resource. * Add Opregions for PMIC, * TI_PMIC_POWER_OPREGION * TI_PMIC_VR_VAL_OPREGION * TI_PMIC_CLK_OPREGION * TI_PMIC_CLK_FREQ_OPREGION * Add power resources for sensors and VCM, * OVTH for CAM0 * OVFI for CAM1 * VCMP for VCM * Implement _ON and _OFF methods for senor and VCM module's power on and power off sequences. Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/acpi/mipi_camera.asl 1 file changed, 411 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/20054/1 diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl index 3806ec8..1a7a98e 100644 --- a/src/mainboard/google/poppy/acpi/mipi_camera.asl +++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl @@ -26,6 +26,349 @@ Return (0x0F) } + /* Marks the availability of the region */ + Name (AVBL, Zero) + Method (_REG, 2, NotSerialized) + { + If (LEqual (Arg0, 0x08)) + { + Store (Arg1, AVBL) + } + } + + OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2) + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x004D, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", + 0x00, ResourceConsumer,,) + { + 4 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", + 0x00, ResourceConsumer,,) + { + 5 + } + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC", + 0x00, ResourceConsumer,,) + { + 9 + } + }) + + /* PMIC operation regions */ + /* 0xB0 == TI_PMIC_POWER_OPREGION_ID */ + OperationRegion (PWR1, 0xB0, Zero, 0x0100) + Field(PWR1, DWordAcc, NoLock, Preserve) + { + VSIO, 32, + VCMC, 32, + VAX1, 32, + VAX2, 32, + VACT, 32, + VDCT, 32, + } + + /* 0xB1 == TI_PMIC_VR_VAL_OPREGION_ID */ + OperationRegion (PWR2, 0xB1, Zero, 0x0100) + Field(PWR2, DWordAcc, NoLock, Preserve) + { + SIOV, 32, + IOVA, 32, + VCMV, 32, + AX1V, 32, + AX2V, 32, + ACVA, 32, + DCVA, 32, + } + + /* 0xB2 == TI_PMIC_CLK_OPREGION_ID */ + OperationRegion (CLKC, 0xB2, Zero, 0x0100) + Field(CLKC, DWordAcc, NoLock, Preserve) + { + PCTL, 32, + PCT2, 32, + CFG1, 32, + CFG2, 32, + } + + /* 0xB3 == TI_PMIC_CLK_FREQ_OPREGION_ID */ + OperationRegion (CLKF, 0xB3, Zero, 0x0100) + Field(CLKF, DWordAcc, NoLock, Preserve) + { + PDV2, 32, + BODI, 32, + BUDI, 32, + PSWR, 32, + XTDV, 32, + PLDV, 32, + PODV, 32, + } + + /* CLE0 and CLE1 are used to determine if both the are + enabled are disabled. */ + Mutex(MUTC, 0) + Name (CLE0, 0) + Name (CLE1, 0) + Method (CLKE, 0, Serialized){ + Store(0, Local0) + /* save Acquire result so we can check for + Mutex acquired */ + Store (Acquire(MUTC, 1000), Local0) + /* check for Mutex acquired */ + If (LEqual(Local0, Zero)) { + /* Enable clocks only when a sensor is turned on and + both the clocks are disabled */ + If (LNot(LOr(CLE0, CLE1))) { + BODI = 3 + BUDI = 2 + PSWR = 19 + XTDV = 170 + PLDV = 32 + PODV = 1 + PDV2 = 1 + /* Enable clocks for both the sensors */ + CFG2 = 5 + CFG1 = 10 + PCTL = 209 + Sleep(1) + } + Release(MUTC) + } + } + + /* Clocks need to be disabled only if both the sensors are + turned off */ + Method (CLKD, 0, Serialized) { + OR (CLE0, CLE1, Local0) + If (LNot(Local0)) { + BODI = 0 + BUDI = 0 + PSWR = 0 + XTDV = 0 + PLDV = 0 + PODV = 0 + PDV2 = 0 + /* Disable clocks for both the sensors */ + CFG2 = 0 + CFG1 = 0 + PCTL = 0 + } + } + + /* Reference count for VSIO */ + Mutex(MUTV, 0) + Name (VSIC, 0) + Method (DOVD, 1, Serialized){ + Store(0, Local0) + /* Save Acquire result so we can check for + Mutex acquired */ + Store (Acquire(MUTV, 1000), Local0) + /* Check for Mutex acquired */ + If (LEqual(Local0, Zero)) { + /* Turn off VSIO */ + If (LEqual(Arg0, Zero)) { + /* Decrement only if VSIC > 0 */ + if (LGreater(VSIC, 0)) { + Decrement(VSIC) + If (LEqual(VSIC, Zero)) { + VSIO = 0 + } + } + } ElseIf (LEqual(Arg0, 2)) { + /* Increment only if VSIC < 2 */ + If (LLess(VSIC, 2)) { + /* Turn on VSIO */ + If (LEqual(VSIC, Zero)) { + VSIO = 3 + } + Increment(VSIC) + } + } + + Release(MUTV) + } + } + + /* Power resource methods for CAM0 */ + PowerResource (OVTH, 0, 0) { + Name (STA, 0) + Method (_ON, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 0)) { + /* Enable VSIO regulator + + daisy chain */ + DOVD(1) + + if (LNotEqual(IOVA, 52)) { + /* Set VSIO value as 1.8006 V */ + IOVA = 52 + } + if (LNotEqual(SIOV, 52)) { + /* Set VSIO value as 1.8006 V */ + SIOV = 52 + } + Sleep(3) + + VACT = 1 + if (LNotEqual(ACVA, 109)) { + /* Set ANA at 2.8152V */ + ACVA = 109 + } + Sleep(3) + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE0 = 1 + + VDCT = 1 + if (LNotEqual(DCVA, 12)) { + DCVA = 12 /* Set CORE at 1.2V */ + } + Sleep(3) + \_SB.PCI0.I2C2.CAM0.CRST(1) + + STA = 1 + } + } + } + + Method (_OFF, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 1)) { + Sleep(2) + CLE0 = 0 + \_SB.PCI0.I2C2.PMIC.CLKD() + Sleep(2) + \_SB.PCI0.I2C2.CAM0.CRST(0) + Sleep(3) + VDCT = 0 + Sleep(3) + VACT = 0 + Sleep(1) + DOVD(0) + Sleep(1) + } + } + STA = 0 + } + Method (_STA, 0, NotSerialized) { + Return (STA) + } + } + + /* Power resource methods for CAM1 */ + PowerResource (OVFI, 0, 0) { + Name (STA, 0) + Method (_ON, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 0)) { + VAX2 = 1 /* Enable VAUX2 */ + + if (LNotEqual(AX2V, 52)) { + /* Set VAUX2 as 1.8006 V */ + AX2V = 52 + } + Sleep(1) + + \_SB.PCI0.I2C2.PMIC.CLKE() + CLE1 = 1 + + VAX1 = 1 /* Enable VAUX1 */ + if (LNotEqual(AX1V, 19)) { + /* Set VAUX1 as 1.2132 V */ + AX1V = 19 + } + Sleep(3) + + \_SB.PCI0.I2C4.CAM1.CGP4(1) + Sleep(3) + + \_SB.PCI0.I2C4.CAM1.CGP5(1) + Sleep(3) + STA = 1 + } + } + } + + Method (_OFF, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 1)) { + Sleep(2) + CLE1 = 0 + \_SB.PCI0.I2C2.PMIC.CLKD() + Sleep(2) + \_SB.PCI0.I2C4.CAM1.CGP5(0) + Sleep(3) + VAX1 = 0 + Sleep(1) + \_SB.PCI0.I2C4.CAM1.CGP4(0) + Sleep(1) + VAX2 = 0 + Sleep(1) + + } + STA = 0 + } + } + Method (_STA, 0, NotSerialized) { + Return (STA) + } + } + + /* Power resource methods for VCM */ + PowerResource (VCMP, 0, 0) { + Name (STA, 0) + Method (_ON, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 0)) { + /* Enable VSIO regulator + + daisy chain */ + DOVD(1) + if (LNotEqual(IOVA, 52)) { + /* Set VSIO value as 1.8006 V */ + IOVA = 52 + } + if (LNotEqual(SIOV, 52)) { + /* Set VSIO value as 1.8006 V */ + SIOV = 52 + } + Sleep(3) + + VCMC = 1 /* Enable VCM regulator */ + if (LNotEqual(VCMV, 109)) { + /* Set VCM value at 2.8152 V */ + VCMV = 109 + } + Sleep(3) + + STA = 1 + } + } + } + Method (_OFF, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 1)) { + VCMC = 0 /* Disable regulator */ + Sleep(1) + DOVD(0) /* Disable regulator */ + Sleep(1) + STA = 0 + } + } + } + + Method (_STA, 0, NotSerialized) { + Return (STA) + } + } + } } @@ -52,6 +395,31 @@ 0x00, ResourceConsumer, , ) }) + + Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve) + { + Connection + ( + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C2.PMIC", 0x00, + ResourceConsumer,,) + { + 9 + } + ), + GRST, 1, + } + + /* Set or clear GRST GPIO */ + Method (CRST, 1, Serialized) + { + GRST = Arg0 + } + + Name (_PR0, Package () { ^^I2C2.PMIC.OVTH }) + Name (_PR3, Package () { ^^I2C2.PMIC.OVTH }) + /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { @@ -135,6 +503,8 @@ ) }) + Name (_PR0, Package () { ^PMIC.VCMP }) + Name (_PR3, Package () { ^PMIC.VCMP }) } } @@ -162,6 +532,47 @@ ) }) + Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve) + { + Connection + ( + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C2.PMIC", 0x00, + ResourceConsumer,,) + { + 4 + } + ), + GPO4, 1, + Connection + ( + GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, + IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C2.PMIC", 0x00, + ResourceConsumer,,) + { + 5 + } + ), + GPO5, 1, + } + + /* Set or clear GPO4 GPIO */ + Method (CGP4, 1, Serialized) + { + GPO4 = Arg0 + } + + /* Set or clear GPO5 GPIO */ + Method (CGP5, 1, Serialized) + { + GPO5 = Arg0 + } + + Name (_PR0, Package () { ^^I2C2.PMIC.OVFI }) + Name (_PR3, Package () { ^^I2C2.PMIC.OVFI }) + /* Port0 of CAM1 is connected to port1 of CIO2 device */ Name (_DSD, Package () { ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), -- To view, visit https://review.coreboot.org/20054 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d Gerrit-Change-Number: 20054 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/google/poppy:[WIP] Add ports and endpoints configuration ...
by V Sowmya (Code Review) 07 Jun '17

07 Jun '17

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/20053 Change subject: mb/google/poppy:[WIP] Add ports and endpoints configuration for sensor and CIO2 devices ...................................................................... mb/google/poppy:[WIP] Add ports and endpoints configuration for sensor and CIO2 devices Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- A src/mainboard/google/poppy/acpi/ipu_mainboard.asl M src/mainboard/google/poppy/acpi/mipi_camera.asl M src/mainboard/google/poppy/dsdt.asl 3 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/20053/2 diff --git a/src/mainboard/google/poppy/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..4938f1c --- /dev/null +++ b/src/mainboard/google/poppy/acpi/ipu_mainboard.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.CIO2) +{ + /* Define two ports for CIO2 device where endpoint of port0 + is connected to CAM0 and endpoint of port1 is connected to CAM1 */ + + Name (_DSD, Package () { + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + Package () { "port1", "PRT1" }, + } + }) + + Name (PRT0, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, /* csi 0 */ + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + Name (EP00, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", Package () { 1, 2, 3, 4 } }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.I2C2.CAM0, 0, 0 } + }, + } + }) + + NAME (PRT1, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 1 }, /* csi 1 */ + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint1", "EP10" }, + } + }) + Name (EP10, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", Package () { 1, 2 } }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.I2C4.CAM1, 0, 0 } + }, + } + }) +} diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl index d3db2b2..3806ec8 100644 --- a/src/mainboard/google/poppy/acpi/mipi_camera.asl +++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl @@ -53,6 +53,42 @@ ) }) + /* Port0 of CAM0 is connected to port0 of CIO2 device */ + Name (_DSD, Package () { + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + } + }) + + Name (PRT0, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + + Name (EP00, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", + Package () { 1, 2, 3, 4 } + }, + Package () { "link-frequencies", + Package() { 1190400000, 640000000 } + }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.CIO2, 0, 0 } + }, + } + }) + Method (SSDB, 0, Serialized) { Return (Buffer (0x5E) @@ -90,6 +126,7 @@ } Name (_DEP, Package() {\_SB.PCI0.I2C2.PMIC}) + Name (_CRS, ResourceTemplate () { I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, @@ -116,6 +153,7 @@ } Name (_DEP, Package() {\_SB.PCI0.I2C2.PMIC}) + Name (_CRS, ResourceTemplate () { I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, @@ -124,6 +162,42 @@ ) }) + /* Port0 of CAM1 is connected to port1 of CIO2 device */ + Name (_DSD, Package () { + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + } + }) + + Name (PRT0, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + + Name (EP00, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", + Package () { 1, 2 } + }, + Package () { "link-frequencies", + Package() { 844800000 } + }, + Package () { "remote-endpoint", + Package() { \_SB.PCI0.CIO2, 1, 0 } + }, + } + }) + Method (SSDB, 0, Serialized) { Return (Buffer (0x5E) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 5008e05..89ca5c6 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -51,6 +51,7 @@ /* MIPI camera */ #include "acpi/mipi_camera.asl" + #include "acpi/ipu_mainboard.asl" /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> -- To view, visit https://review.coreboot.org/20053 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Gerrit-Change-Number: 20053 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/google/poppy:[WIP] Add MIPI camera support.
by V Sowmya (Code Review) 07 Jun '17

07 Jun '17

Hello Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19621 to look at the new patch set (#5). Change subject: mb/google/poppy:[WIP] Add MIPI camera support. ...................................................................... mb/google/poppy:[WIP] Add MIPI camera support. This patch adds mipi_camera.asl, * Add TPS68470 PMIC related ACPI objects. * Add OV cameras related ACPI objects. * Add Dongwoon AF DAC related ACPI objects. * SSDB: Sensor specific database for camera sensor. * CAMD: ACPI object to specify the camera device type. Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- A src/mainboard/google/poppy/acpi/mipi_camera.asl M src/mainboard/google/poppy/dsdt.asl 2 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/19621/5 -- To view, visit https://review.coreboot.org/19621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Gerrit-Change-Number: 19621 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy:[WIP] Remove MIPI camera support from device...
by V Sowmya (Code Review) 07 Jun '17

07 Jun '17

V Sowmya has uploaded a new patch set (#4). ( https://review.coreboot.org/19619 ) Change subject: mb/google/poppy:[WIP] Remove MIPI camera support from devicetree.cb ...................................................................... mb/google/poppy:[WIP] Remove MIPI camera support from devicetree.cb Remove MIPI camera related register entries from devicetree.cb. Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 2 files changed, 2 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19619/4 -- To view, visit https://review.coreboot.org/19619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Gerrit-Change-Number: 19619 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2017