coreboot-gerrit June 2017

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Change in coreboot[master]: rx6110sa: Add more chip configuration options to chip
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20084 ) Change subject: rx6110sa: Add more chip configuration options to chip ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10745/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55065/ : SUCCESS -- To view, visit https://review.coreboot.org/20084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Gerrit-Change-Number: 20084 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 08:04:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [UNTESTED]mb/apple/macbook21: Add ACPI C3 state
by Arthur Heymans (Code Review) 07 Jun '17

07 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20083 to look at the new patch set (#2). Change subject: [UNTESTED]mb/apple/macbook21: Add ACPI C3 state ...................................................................... [UNTESTED]mb/apple/macbook21: Add ACPI C3 state This needs the clockgen to be reconfigured. Values are taken while running vendor firmware (smbus device at offset 0x69 using smbus block read) Change-Id: I0b391825a0e79bddb9aa4c914153a9bac2f20155 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbook21/mainboard.c 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/20083/2 -- To view, visit https://review.coreboot.org/20083 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0b391825a0e79bddb9aa4c914153a9bac2f20155 Gerrit-Change-Number: 20083 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/apple/macbook21: Add ACPI C3 state
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20083 ) Change subject: mb/apple/macbook21: Add ACPI C3 state ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10741/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55061/ : UNSTABLE -- To view, visit https://review.coreboot.org/20083 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0b391825a0e79bddb9aa4c914153a9bac2f20155 Gerrit-Change-Number: 20083 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 08:02:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge: Fill in acpi_name
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20085 ) Change subject: nb/intel/sandybridge: Fill in acpi_name ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10743/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55063/ : SUCCESS -- To view, visit https://review.coreboot.org/20085 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Gerrit-Change-Number: 20085 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 08:00:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: rx6110sa: Add more chip configuration options to chip
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20084 ) Change subject: rx6110sa: Add more chip configuration options to chip ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55062/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10742/ : SUCCESS -- To view, visit https://review.coreboot.org/20084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Gerrit-Change-Number: 20084 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 07:58:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Fill in acpi_name
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20086 ) Change subject: sb/intel/bd82x6x: Fill in acpi_name ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10744/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/55064/ : FAILURE -- To view, visit https://review.coreboot.org/20086 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Gerrit-Change-Number: 20086 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 07:56:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Fill in acpi_name
by Patrick Rudolph (Code Review) 07 Jun '17

07 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20086 Change subject: sb/intel/bd82x6x: Fill in acpi_name ...................................................................... sb/intel/bd82x6x: Fill in acpi_name Fill in acpi_name to return proper ACPI names. To be used with ssdt generators. Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/bd82x6x/usb_xhci.c 7 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20086/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index c122d2a..0e974ba 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -331,6 +331,11 @@ pci_write_config8(dev, 0x43, reg8); } +static const char *azalia_acpi_name(device_t dev) +{ + return "HDEF"; +} + static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -353,6 +358,7 @@ .init = azalia_init, .scan_bus = 0, .ops_pci = &azalia_pci_ops, + .acpi_name = azalia_acpi_name, }; static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c9fee89..209c8ed 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -814,6 +814,11 @@ fadt->x_gpe1_blk.addrh = 0x0; } +static const char *lpc_acpi_name(device_t dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); @@ -841,6 +846,7 @@ .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 627b6f7..07f8138 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -297,6 +297,29 @@ pch_pcie_pm_late(dev); } +static const char *pch_pcie_acpi_name(device_t dev) +{ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0x1c, 0): + return "RP01"; + case PCI_DEVFN(0x1c, 1): + return "RP02"; + case PCI_DEVFN(0x1c, 2): + return "RP03"; + case PCI_DEVFN(0x1c, 3): + return "RP04"; + case PCI_DEVFN(0x1c, 4): + return "RP05"; + case PCI_DEVFN(0x1c, 5): + return "RP06"; + case PCI_DEVFN(0x1c, 6): + return "RP07"; + case PCI_DEVFN(0x1c, 7): + return "RP08"; + } + return NULL; +} + static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ @@ -321,6 +344,7 @@ .disable = pch_pcie_disable, .enable = pch_pcie_enable, .scan_bus = pch_pciexp_scan_bridge, + .acpi_name = pch_pcie_acpi_name, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index d217a04..ac4945d 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -244,6 +244,11 @@ } } +static const char *sata_acpi_name(device_t dev) +{ + return "SATA"; +} + static void sata_fill_ssdt(device_t dev) { config_t *config = dev->chip_info; @@ -264,6 +269,7 @@ .enable = sata_enable, .scan_bus = 0, .ops_pci = &sata_pci_ops, + .acpi_name = sata_acpi_name, }; static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 5778e25..c450d9b 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -143,6 +143,11 @@ res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); } +static const char *smbus_acpi_name(device_t dev) +{ + return "SBUS"; +} + static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, @@ -151,6 +156,7 @@ .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, + .acpi_name = smbus_acpi_name, }; static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 }; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 2712a5b..42d7a83 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -94,6 +94,17 @@ pci_write_config8(dev, 0x80, access_cntl); } +static const char *usb_ehci_acpi_name(device_t dev) +{ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0x1a, 0): + return "EHC2"; + case PCI_DEVFN(0x1d, 0): + return "EHC1"; + } + return NULL; +} + static struct pci_operations lops_pci = { .set_subsystem = &usb_ehci_set_subsystem, }; @@ -105,6 +116,7 @@ .init = usb_ehci_init, .scan_bus = 0, .ops_pci = &lops_pci, + .acpi_name = usb_ehci_acpi_name, }; static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 74deb52..1aeb864 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -51,6 +51,11 @@ printk(BIOS_DEBUG, "done.\n"); } +static const char *xhci_acpi_name(device_t dev) +{ + return "XHC"; +} + static void xhci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -73,6 +78,7 @@ .init = usb_xhci_init, .scan_bus = 0, .ops_pci = &xhci_pci_ops, + .acpi_name = xhci_acpi_name, }; static const unsigned short pci_device_ids[] = { 0x1e31, 0 }; -- To view, visit https://review.coreboot.org/20086 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6 Gerrit-Change-Number: 20086 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge: Fill in acpi_name
by Patrick Rudolph (Code Review) 07 Jun '17

07 Jun '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20085 Change subject: nb/intel/sandybridge: Fill in acpi_name ...................................................................... nb/intel/sandybridge: Fill in acpi_name Fill in acpi_name to return proper ACPI names. To be used with ssdt generators. Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/20085/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 868a961..c74a2b7 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -675,6 +675,11 @@ return current; } +static const char *gma_acpi_name(device_t dev) +{ + return "GFX0"; +} + /* called by pci set_vga_bridge function */ static void gma_func0_disable(struct device *dev) { @@ -702,6 +707,7 @@ .enable = 0, .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, .write_acpi_tables = gma_write_acpi_tables, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5c5f41a..a8826d2 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -242,6 +242,21 @@ assign_resources(dev->link_list); } +static const char *northbridge_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): return "MCHC"; + } + + return NULL; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -252,8 +267,9 @@ .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_name = northbridge_acpi_name, }; static void mc_read_resources(device_t dev) -- To view, visit https://review.coreboot.org/20085 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9 Gerrit-Change-Number: 20085 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: drvs/intel/wifi/wifi: Fix regression
by build bot (Jenkins) (Code Review) 07 Jun '17

07 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20082 ) Change subject: drvs/intel/wifi/wifi: Fix regression ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10740/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55060/ : SUCCESS -- To view, visit https://review.coreboot.org/20082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f Gerrit-Change-Number: 20082 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jun 2017 07:55:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: rx6110sa: Add more chip configuration options to chip
by Werner Zeh (Code Review) 07 Jun '17

07 Jun '17

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/20084 Change subject: rx6110sa: Add more chip configuration options to chip ...................................................................... rx6110sa: Add more chip configuration options to chip The RTC RX6110SA has several configuration options which might be interesting to set. To make this set up independent of the driver itself but let it still be configurable on mainboard level, add more configuration options to the chip driver. Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/chip.h M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/rx6110sa/rx6110sa.h 3 files changed, 72 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/20084/1 diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index b90a529..76db780 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -23,4 +23,17 @@ unsigned char user_year; /* User year to set */ unsigned char set_user_date; /* Use user date from device tree */ unsigned char cof_selection; /* Set up "clock out" frequency */ + unsigned char timer_clk; /* Set up timer clock */ + unsigned char timer_irq_en; /* Interrupt generation on timer */ + unsigned short timer_preset; /* Preset value for the timer */ + unsigned char timer_mode; /* Set the timer mode of operation */ + unsigned char timer_en; /* Enable timer operation */ + unsigned char irq_output_pin; /* 0: IRQ2 pin used, 1: IRQ1 pin used */ + unsigned char fout_output_pin; /* 0: IRQ2, 1: IRQ1, 2: DO/FOUT */ + unsigned char enable_1hz_out; /* If set enables 1 Hz output on IRQ1 */ + unsigned char pmon_sampling; /* Select power monitor sampling time */ + /* The following two bits set the power monitor and backup mode. */ + unsigned char bks_on; + unsigned char bks_off; + unsigned char iocut_en; /* Disable backup of I/O circuit. */ }; diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 9d60bdb..415821f 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -88,33 +88,52 @@ struct drivers_i2c_rx6110sa_config *config = dev->chip_info; uint8_t reg; - /* Do a dummy read first. */ - reg = rx6110sa_read(dev, SECOND_REG); - + /* Do a dummy read first as desired in datasheet. */ + rx6110sa_read(dev, SECOND_REG); + /* + * Set battery backup mode and power monitor sampling time every go to + * make sure that the right mode is used as it directly influence the + * backup current consumption and therefore the backup time. + */ + reg = (config->pmon_sampling & PMON_SAMPL_MASK) | + (!!config->bks_off << 2) | (!!config->bks_on << 3) | + (!!config->iocut_en << 4); + rx6110sa_write(dev, BATTERY_BACKUP_REG, reg); /* * Check VLF-bit which indicates the RTC data loss, such as due to a * supply voltage drop. */ reg = rx6110sa_read(dev, FLAG_REGISTER); - if (!(reg & VLF_BIT)) /* No voltage low detected, everything is well. */ return; - /* * Voltage low detected, initialize RX6110 SA again. * Set first some registers to known state. */ - rx6110sa_write(dev, BATTERY_BACKUP_REG, 0x00); rx6110sa_write(dev, RESERVED_BIT_REG, RTC_INIT_VALUE); rx6110sa_write(dev, DIGITAL_REG, 0x00); - rx6110sa_write(dev, IRQ_CONTROL_REG, 0x00); + reg = (!!config->enable_1hz_out << 4) | + (!!config->irq_output_pin << 2) | + (config->fout_output_pin & FOUT_OUTPUT_PIN_MASK); + rx6110sa_write(dev, IRQ_CONTROL_REG, reg); /* Clear timer enable bit and set frequency of clock output. */ - reg = rx6110sa_read(dev, EXTENSION_REG); reg &= ~(FSEL_MASK | TE_BIT); reg |= (config->cof_selection << 6); + if (config->timer_en && config->timer_preset) { + /* Timer needs to be in stop mode prior to program it. */ + rx6110sa_write(dev, EXTENSION_REG, reg); + reg &= ~TSEL_MASK; + /* Program the timer preset value. */ + rx6110sa_write(dev, TMR_COUNTER_0_REG, + config->timer_preset & 0xff); + rx6110sa_write(dev, TMR_COUNTER_1_REG, + (config->timer_preset >> 8) & 0xff); + /* Set Timer Enable bit and the timer clock value. */ + reg |= (TE_BIT | (config->timer_clk & TSEL_MASK)); + } rx6110sa_write(dev, EXTENSION_REG, reg); /* Clear voltage low detect bit. */ @@ -140,7 +159,9 @@ rx6110sa_write(dev, MINUTE_REG, 0); rx6110sa_write(dev, SECOND_REG, 0); /* Start oscillator again as the RTC is set up now. */ - rx6110sa_write(dev, CTRL_REG, 0x00); + reg = (!!config->timer_irq_en << 4) | + (config->timer_mode & TMR_MODE_MASK); + rx6110sa_write(dev, CTRL_REG, reg); } static struct device_operations rx6110sa_ops = { diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 99527e0..a7d29dc 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -38,6 +38,7 @@ #define EXTENSION_REG 0x1D #define TE_BIT (1 << 4) #define FSEL_MASK 0xC0 +#define TSEL_MASK 0x07 #define FLAG_REGISTER 0x1E #define VLF_BIT (1 << 1) #define CTRL_REG 0x1F @@ -46,9 +47,15 @@ #define UIE_BIT (1 << 5) #define STOP_BIT (1 << 6) #define TEST_BIT (1 << 7) +#define TMR_MODE_MASK 0x03 +#define TMR_MODE_NORM_BACKUP 0x00 +#define TMR_MODE_NORM_ONLY 0x01 +#define TMR_MODE_BACKUP_ONLY 0x03 #define DIGITAL_REG 0x30 #define BATTERY_BACKUP_REG 0x31 +#define PMON_SAMPL_MASK 0x03 #define IRQ_CONTROL_REG 0x32 +#define FOUT_OUTPUT_PIN_MASK 0x03 /* Define CLKOUT frequency divider values valid for parameter cof_selection */ #define COF_OFF 0x00 @@ -56,4 +63,26 @@ #define COF_1024_HZ 0x02 #define COF_32768_HZ 0x03 +/* Define valid clock rates for the internal timer */ +#define TMR_CLK_4096_HZ 0x00 +#define TMR_CLK_64_HZ 0x01 +#define TMR_CLK_1_HZ 0x02 +#define TMR_CLK_1_60_HZ 0x03 +#define TMR_CLK_1_3600_HZ 0x04 + +/* + * Define possible power monitor sampling times. This value decides for how + * long the power supply is sampled every second to detect a + * power down condition. + */ +#define PMON_SAMPL_2_MS 0x00 +#define PMON_SAMPL_16_MS 0x01 +#define PMON_SAMPL_128_MS 0x02 +#define PMON_SAMPL_256_MS 0x03 + +/* Define on which pin of the RTC the generated square wave will be driven. */ +#define FOUT_IRQ2 0x00 /* IRQ2 pin used for Fout */ +#define FOUT_IRQ1 0x01 /* IRQ1 pin used for Fout */ +#define FOUT_DO_FOUT 0x02 /* DO/FOUT pin used for Fout */ + #endif /* _I2C_RX6110SA_H_ */ -- To view, visit https://review.coreboot.org/20084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Gerrit-Change-Number: 20084 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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coreboot-gerrit June 2017