coreboot-gerrit June 2017

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Change in coreboot[master]: arch/*: Update Kconfig symbol usage
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20005 ) Change subject: arch/*: Update Kconfig symbol usage ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10893/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55219/ : SUCCESS -- To view, visit https://review.coreboot.org/20005 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85 Gerrit-Change-Number: 20005 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 22:37:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/gm45: Add SMBIOS table 17 generation
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20119 ) Change subject: nb/intel/gm45: Add SMBIOS table 17 generation ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10892/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55218/ : SUCCESS -- To view, visit https://review.coreboot.org/20119 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16c005baee900b56a4b0c76bb880105c06c518a7 Gerrit-Change-Number: 20119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 21:18:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/gm45: Add SMBIOS table 17 generation
by Arthur Heymans (Code Review) 08 Jun '17

08 Jun '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20119 Change subject: nb/intel/gm45: Add SMBIOS table 17 generation ...................................................................... nb/intel/gm45: Add SMBIOS table 17 generation Some things like DIMM number and memory type are hardcoded due to raminit not supporting multiple DIMMs per channel and ddr3. TESTED on Thinkpad X200. Change-Id: I16c005baee900b56a4b0c76bb880105c06c518a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/raminit.c 5 files changed, 59 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20119/1 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 31a80a4..561893d 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -168,6 +168,8 @@ cbmem_initted = !cbmem_recovery(s3resume); + fill_smbios17(&sysinfo); + romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 49c5528..1a3edb9 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -159,6 +159,8 @@ cbmem_initted = !cbmem_recovery(s3resume); + fill_smbios17(&sysinfo); + romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 720f628..28ac41b 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -189,6 +189,8 @@ cbmem_initted = !cbmem_recovery(s3resume); + fill_smbios17(&sysinfo); + romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 34f734c..85ce363 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -415,6 +415,7 @@ void enter_raminit_or_reset(void); void get_gmch_info(sysinfo_t *); void raminit(sysinfo_t *, int s3resume); +void fill_smbios17(const sysinfo_t *ctrl); void raminit_thermal(const sysinfo_t *); void init_igd(const sysinfo_t *const); void init_pm(const sysinfo_t *, int do_freq_scaling_cfg); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 30e9297..d4f2111 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -18,10 +18,14 @@ #include <stdlib.h> #include <arch/cpu.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <device/device.h> +#include <memory_info.h> +#include <smbios.h> #include <spd.h> +#include <string.h> #include <console/console.h> #include <lib.h> #include <delay.h> @@ -1705,6 +1709,54 @@ MCHBAR32(0x15f0) |= (1 << 10); } +void fill_smbios17(const sysinfo_t *ctrl) +{ + struct memory_info *mem_info; + int channel; + struct dimm_info *dimm; + u16 ddr_freq = 0; + + switch (ctrl->selected_timings.mem_clock) { + case MEM_CLOCK_533MHz: + ddr_freq = 533; + break; + case MEM_CLOCK_400MHz: + ddr_freq = 400; + break; + case MEM_CLOCK_333MHz: + ddr_freq = 333; + break; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + /* Assumes one slot per channel */ + FOR_EACH_POPULATED_CHANNEL(ctrl->dimms, channel) { + dimm = &(mem_info->dimm[mem_info->dimm_cnt]); + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->ddr_frequency = ddr_freq; + dimm->dimm_size = ctrl->dimms[channel].rank_capacity_mb * + ctrl->dimms[channel].ranks; + dimm->channel_num = channel; + dimm->rank_per_dimm = ctrl->dimms[channel].ranks; + dimm->dimm_num = 0; + /* We skip module part number, manufacturer id since SPD */ + /* reading is slow */ + dimm->mod_type = ctrl->dimms[channel].card_type; + dimm->bus_width = 0x3; /* 64 bit ? */ + mem_info->dimm_cnt++; + } +} + void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; -- To view, visit https://review.coreboot.org/20119 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16c005baee900b56a4b0c76bb880105c06c518a7 Gerrit-Change-Number: 20119 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: lib/spd_bin: Print out correct SMBus SPD address in dump_spd...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20118 ) Change subject: lib/spd_bin: Print out correct SMBus SPD address in dump_spd_info ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/55217/ : SUCCESS -- To view, visit https://review.coreboot.org/20118 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Gerrit-Change-Number: 20118 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 20:39:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lib/spd_bin: Print out correct SMBus SPD address in dump_spd...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20118 ) Change subject: lib/spd_bin: Print out correct SMBus SPD address in dump_spd_info ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55216/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10891/ : SUCCESS -- To view, visit https://review.coreboot.org/20118 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Gerrit-Change-Number: 20118 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 20:31:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lib/spd_bin: Print out correct SMBus SPD address in dump_spd...
by Furquan Shaikh (Code Review) 08 Jun '17

08 Jun '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20118 Change subject: lib/spd_bin: Print out correct SMBus SPD address in dump_spd_info ...................................................................... lib/spd_bin: Print out correct SMBus SPD address in dump_spd_info With change dd82edc388 (lib/spd_bin: make SMBus SPD addresses an input), SMBus SPD addresses are accepted from the mainboard and not calculated within the spd_bin library routines. Use the addr_map values to print correct address in dump_spd_info. Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/20118/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 3e26004..a9f6a36 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -29,7 +29,7 @@ for (i = 0; i < CONFIG_DIMM_MAX; i++) if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { - printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); + printk(BIOS_DEBUG, "SPD @ 0x%02X\n", blk->addr_map[i]); print_spd_info(blk->spd_array[i]); } } -- To view, visit https://review.coreboot.org/20118 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iff37e382aeac9704f74bafc2ecb27f14c478723f Gerrit-Change-Number: 20118 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/55215/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10890/ : SUCCESS -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-Change-Number: 19958 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 19:48:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10889/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55213/ : SUCCESS -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-Change-Number: 19958 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 19:16:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/glkrvp: configure RAPL PL1 for GLK
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19746 ) Change subject: mainboard/intel/glkrvp: configure RAPL PL1 for GLK ...................................................................... Patch Set 9: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55214/ : FAILURE -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-Change-Number: 19746 Gerrit-PatchSet: 9 Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 19:16:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: configure RAPL PL1 for GLK
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19746 ) Change subject: soc/intel/apollolake: configure RAPL PL1 for GLK ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55212/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10888/ : SUCCESS -- To view, visit https://review.coreboot.org/19746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665 Gerrit-Change-Number: 19746 Gerrit-PatchSet: 8 Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 18:03:09 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017