coreboot-gerrit June 2017

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 35: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10899/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55225/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-Change-Number: 19759 Gerrit-PatchSet: 35 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 23:52:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake[WIP]
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19949 ) Change subject: soc/intel/apollolake: Use common gpio for apollolake[WIP] ...................................................................... Patch Set 21: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55226/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10900/ : SUCCESS -- To view, visit https://review.coreboot.org/19949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Gerrit-Change-Number: 19949 Gerrit-PatchSet: 21 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 23:48:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 34: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10898/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55224/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-Change-Number: 19759 Gerrit-PatchSet: 34 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 23:23:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add USB port number information to wake s...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20122 ) Change subject: soc/intel/skylake: Add USB port number information to wake source ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10897/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55223/ : SUCCESS -- To view, visit https://review.coreboot.org/20122 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Gerrit-Change-Number: 20122 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 23:02:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: elog: Add more detailed wake source events for USB2.0/3.0 po...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20121 ) Change subject: elog: Add more detailed wake source events for USB2.0/3.0 port wake ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10895/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55221/ : SUCCESS -- To view, visit https://review.coreboot.org/20121 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0b495234d6e498d5c64ba4dd186440cd7a1c5c6 Gerrit-Change-Number: 20121 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 22:56:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add USB port number information to wake s...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20122 ) Change subject: soc/intel/skylake: Add USB port number information to wake source ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/55222/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10896/ : SUCCESS -- To view, visit https://review.coreboot.org/20122 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Gerrit-Change-Number: 20122 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 22:55:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add USB port number information to wake s...
by Furquan Shaikh (Code Review) 08 Jun '17

08 Jun '17

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/20122 ) Change subject: soc/intel/skylake: Add USB port number information to wake source ...................................................................... soc/intel/skylake: Add USB port number information to wake source USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/elog.c 1 file changed, 120 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/20122/2 -- To view, visit https://review.coreboot.org/20122 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Gerrit-Change-Number: 20122 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Add USB port number information to wake s...
by Furquan Shaikh (Code Review) 08 Jun '17

08 Jun '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20122 Change subject: soc/intel/skylake: Add USB port number information to wake source ...................................................................... soc/intel/skylake: Add USB port number information to wake source USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CCS bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/elog.c 1 file changed, 120 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/20122/1 diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index d127fcc..4cdcd2c 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -23,6 +23,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> +#include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -36,6 +37,112 @@ } } +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 6 +/* Wake on disconnect enable */ +#define XHCI_STATUS_WDE (1 << 26) +/* Wake on connect enable */ +#define XHCI_STATUS_WCE (1 << 25) +/* Port link status change */ +#define XHCI_STATUS_PLC (1 << 22) +/* Connect status change */ +#define XHCI_STATUS_CSC (1 << 17) +/* Port link status */ +#define XHCI_STATUS_PLS_SHIFT (5) +#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT) +#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) + +static bool pch_xhci_csc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_CSC); +} + +static bool pch_xhci_wake_capable(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_WCE) | + (port_status & XHCI_STATUS_WDE); +} + +static bool pch_xhci_plc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_PLC); +} + +static bool pch_xhci_resume(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; +} + +/* + * Check if a particular USB port caused wake by: + * 1. Change in connect/disconnect status (if enabled) + * 2. USB device activity + * + * Return value: + * 0 = None of the ports caused a wake + * n = Port number that caused the wake + */ +static uint32_t pch_xhci_port_wake_check(uintptr_t base, uint8_t num) +{ + uint8_t i; + uint32_t port_status; + + for (i = 0; i < num; i++, base += 0x10) { + /* Read port status and control register for the port. */ + port_status = read32((void *)base); + + /* + * Check if CSC bit is set and port is capable of wake on + * connect/disconnect to identify if the port caused wake + * event for usb attach/detach. + */ + if (pch_xhci_csc_set(port_status) && + pch_xhci_wake_capable(port_status)) + return i + 1; + + /* + * Check if PLC is set and PLS indicates resume to identify if + * the port caused wake event for usb activity. + */ + if (pch_xhci_plc_set(port_status) && + pch_xhci_resume(port_status)) + return i + 1; + } + return 0; +} + +/* + * Update elog event and instance depending upon the USB2/USB3 port that caused + * the wake event. + */ +static void pch_xhci_update_wake_event(device_t dev, uint32_t *event, + uint32_t *instance) +{ + uintptr_t mmio_base; + + mmio_base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); + + /* USB2 ports */ + *instance = pch_xhci_port_wake_check(mmio_base + + XHCI_USB2_PORT_STATUS_REG, + XHCI_USB2_PORT_NUM); + + if (*instance) { + *event = ELOG_WAKE_SOURCE_PME_XHCI_USB_2; + return; + } + + /* USB3 ports */ + *instance = pch_xhci_port_wake_check(mmio_base + + XHCI_USB3_PORT_STATUS_REG, + XHCI_USB3_PORT_NUM); + + if (*instance) + *event = ELOG_WAKE_SOURCE_PME_XHCI_USB_3; +} + struct pme_status_info { int devfn; uint8_t reg_offset; @@ -43,6 +150,18 @@ }; #define PME_STS_BIT (1 << 15) + +static void pch_log_add_elog_event(const struct pme_status_info *info, + device_t dev) +{ + uint32_t instance = 0; + uint32_t event = info->elog_event; + + if (info->devfn == PCH_DEVFN_XHCI) + pch_xhci_update_wake_event(dev, &event, &instance); + + elog_add_event_wake(event, instance); +} static void pch_log_pme_internal_wake_source(void) { @@ -87,7 +206,7 @@ if ((val == 0xFFFF) || !(val & PME_STS_BIT)) continue; - elog_add_event_wake(pme_status_info[i].elog_event, 0); + pch_log_add_elog_event(&pme_status_info[i], dev); dev_found = true; } -- To view, visit https://review.coreboot.org/20122 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Gerrit-Change-Number: 20122 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: elog: Add more detailed wake source events for USB2.0/3.0 po...
by Furquan Shaikh (Code Review) 08 Jun '17

08 Jun '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20121 Change subject: elog: Add more detailed wake source events for USB2.0/3.0 port wake ...................................................................... elog: Add more detailed wake source events for USB2.0/3.0 port wake BUG=b:37088992 Change-Id: If0b495234d6e498d5c64ba4dd186440cd7a1c5c6 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/include/elog.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/20121/1 diff --git a/src/include/elog.h b/src/include/elog.h index c11ff2a..ecda87d 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -145,6 +145,8 @@ #define ELOG_WAKE_SOURCE_PME_CSE3 0x1a #define ELOG_WAKE_SOURCE_PME_XHCI 0x1b #define ELOG_WAKE_SOURCE_PME_XDCI 0x1c +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d +#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e struct elog_event_data_wake { u8 source; -- To view, visit https://review.coreboot.org/20121 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If0b495234d6e498d5c64ba4dd186440cd7a1c5c6 Gerrit-Change-Number: 20121 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 08 Jun '17

08 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 33: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10894/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/55220/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-Change-Number: 19759 Gerrit-PatchSet: 33 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Jun 2017 22:45:56 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017