Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20125
Change subject: riscv: Update the gcc built-in macro __riscv__
......................................................................
riscv: Update the gcc built-in macro __riscv__
The architecture is determined by __riscv__ in the LZ4_copy8 function
(located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1.
But __riscv__ does not exist.
Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Signed-off-by: wxjstz <wxjstz(a)126.com>
---
M src/commonlib/lz4_wrapper.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/20125/1
diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/lz4_wrapper.c
index e444f2c..c2014cc 100644
--- a/src/commonlib/lz4_wrapper.c
+++ b/src/commonlib/lz4_wrapper.c
@@ -48,6 +48,7 @@
/* ARM32 needs to be a special snowflake to prevent GCC from coalescing the
* access into LDRD/STRD (which don't support unaligned accesses). */
#ifdef __arm__ /* ARMv < 6 doesn't support unaligned accesses at all. */
+
#if defined(__COREBOOT_ARM_ARCH__) && __COREBOOT_ARM_ARCH__ < 6
int i;
for (i = 0; i < 8; i++)
@@ -67,7 +68,7 @@
: "=m"(*(uint32_t *)(dst + 4))
: [x1]"r"(x1), [dst]"r"(dst));
#endif
-#elif defined(__riscv__)
+#elif defined(__riscv__) || defined(__riscv)
/* RISC-V implementations may trap on any unaligned access. */
int i;
for (i = 0; i < 8; i++)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Gerrit-Change-Number: 20125
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001664
Anonymous Coward #1001664 has uploaded this change for review. ( https://review.coreboot.org/20124
Change subject: riscv: Update register address
......................................................................
riscv: Update register address
I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.
Change-Id: I0a970940c191dae9543dcadb19480efcf5ea6956
Signed-off-by: wxjstz <wxjstz(a)126.com>
---
M src/arch/riscv/virtual_memory.c
M src/mainboard/emulation/spike-riscv/uart.c
2 files changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/20124/1
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 2c440d2..1fff1d1 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -311,11 +311,10 @@
set_csr(medeleg, delegate);
// Enable all user/supervisor-mode counters using
- // v1.9.1 register addresses.
+ // v1.10 register addresses.
// They moved from the earlier spec.
// Until we trust our toolchain use the hardcoded constants.
// These were in flux and people who get the older toolchain
// will have difficult-to-debug failures.
- write_csr(/*mucounteren*/0x320, 7);
- write_csr(/*mscounteren*/0x321, 7);
+ write_csr(/*mcounteren*/0x306, 7);
}
diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
index 57647fe..26ab630 100644
--- a/src/mainboard/emulation/spike-riscv/uart.c
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -20,5 +20,5 @@
uintptr_t uart_platform_base(int idx)
{
- return (uintptr_t) 0x40001000;
+ return (uintptr_t) 0x02100000;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0a970940c191dae9543dcadb19480efcf5ea6956
Gerrit-Change-Number: 20124
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001664