coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/google/poppy: Enable H1 I2C TPM
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19926 ) Change subject: mainboard/google/poppy: Enable H1 I2C TPM ...................................................................... mainboard/google/poppy: Enable H1 I2C TPM Enable H1 I2C TPM in Kconfig and devicetree for poppy. CQ-DEPEND=CL:513513,CL:*381534 BUG=b:36265511 BRANCH=None TEST=Compiles successfully. Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/19926/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index a947ec1..e133f9f 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -14,7 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 - select POPPY_USE_I2C_TPM if BOARD_GOOGLE_SORAKA + select POPPY_USE_I2C_TPM select SOC_INTEL_KABYLAKE if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 51dadda..458f90e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -217,7 +217,12 @@ device i2c 4b on end end end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device i2c 50 on end + end # I2C #1 device pci 15.2 on chip drivers/intel/mipi_camera register "acpi_hid" = ""INT3472"" -- To view, visit https://review.coreboot.org/19926 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I4c6c94fa05abf9f5374505ded5956e879ac79726 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Add detailed information about PME wake s...
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19925 ) Change subject: soc/intel/skylake: Add detailed information about PME wake sources ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10157/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54435/ : SUCCESS -- To view, visit https://review.coreboot.org/19925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/poppy: Add PowerResource for touchscreen de...
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19829 ) Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device ...................................................................... mainboard/google/poppy: Add PowerResource for touchscreen device 1. Do not enable touchscreen device by default in gpio configuration. 2. Select use of PowerResource for touchscreen device in devicetree so that the ACPI subsystem can take care of powering on/off the device. When system enters suspend, touchscreen device is powered off and on resume, it is powered back on. BUG=b:62028489 TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on poppy. Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19829 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/soraka/devicetree.cb 3 files changed, 9 insertions(+), 1 deletion(-) Approvals: Aaron Durbin: Looks good to me, approved Duncan Laurie: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4e3ffaf..51dadda 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -210,6 +210,10 @@ register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "enable_delay_ms" = "250" device i2c 4b on end end end # I2C #0 diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 2be9d0f..a865193 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -174,7 +174,7 @@ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 1, DEEP), + PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index d7fe0e8..7efe413 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -210,6 +210,10 @@ register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "enable_delay_ms" = "250" device i2c 4b on end end end # I2C #0 -- To view, visit https://review.coreboot.org/19829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Add detailed information about PME wake s...
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19925 ) Change subject: soc/intel/skylake: Add detailed information about PME wake sources ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/19925/2/src/soc/intel/skylake/elog.c File src/soc/intel/skylake/elog.c: Line 54: struct pme_status_info pme_status_info[] = { > static const Yeah, PCH_DEV_* does dev_find_slot. That's a good idea - I changed it to PCH_DEVFN_* and added check for NULL. Line 55: {PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA}, > spaces after { and before } Done -- To view, visit https://review.coreboot.org/19925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Add detailed information about PME wake s...
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19925 to look at the new patch set (#3). Change subject: soc/intel/skylake: Add detailed information about PME wake sources ...................................................................... soc/intel/skylake: Add detailed information about PME wake sources Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/elog.c 1 file changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/19925/3 -- To view, visit https://review.coreboot.org/19925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
by Subrata Banik (Code Review) 26 May '17

26 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19793 ) Change subject: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL ...................................................................... Patch Set 2: > It doesn't appear that you pushed an update. yes, i'm in process to address all your review comments and then it stuck. I will fix other issue and push all together. -- To view, visit https://review.coreboot.org/19793 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iace1cf786b08221c3955101186509ac5161c3841 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: device/Kconfig: Clarify ON_DEVICE_ROM_LOAD
by Philippe Mathieu-Daudé (Code Review) 26 May '17

26 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19805 ) Change subject: device/Kconfig: Clarify ON_DEVICE_ROM_LOAD ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/19805 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I898765f79cbf5ccce871a3598b56eda83e5efaca Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: lib/coreboot_tables: Remove weak fill_lb_framebuffer()
by Philippe Mathieu-Daudé (Code Review) 26 May '17

26 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19807 ) Change subject: lib/coreboot_tables: Remove weak fill_lb_framebuffer() ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/19807 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia9e477c2d501b249a632968b5636ac803323895a Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
by Philippe Mathieu-Daudé (Code Review) 26 May '17

26 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19924 ) Change subject: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/19924 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy:[WIP] Clean up MIPI camera support from devi...
by Nicolas Boichat (Code Review) 26 May '17

26 May '17

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/19619 ) Change subject: mb/google/poppy:[WIP] Clean up MIPI camera support from devicetree.cb ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/19619/2//COMMIT_MSG Commit Message: PS2, Line 7: Clean up "remove"? Looks like you're dropping the whole entry from device tree? -- To view, visit https://review.coreboot.org/19619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic6a6a98d4c8ed6cba760eae5fd87bc2a3f15d7d2 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017