coreboot-gerrit May 2017

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Change in coreboot[master]: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19924 ) Change subject: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10149/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54426/ : SUCCESS -- To view, visit https://review.coreboot.org/19924 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ec/librem/ec: Fix offset for Bluetooth enable (BTLE)
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19897 ) Change subject: ec/librem/ec: Fix offset for Bluetooth enable (BTLE) ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54429/ : SUCCESS -- To view, visit https://review.coreboot.org/19897 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ec/librem/ec: Fix offset for Bluetooth enable (BTLE)
by Matt DeVillier (Code Review) 26 May '17

26 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19897 to look at the new patch set (#3). Change subject: ec/librem/ec: Fix offset for Bluetooth enable (BTLE) ...................................................................... ec/librem/ec: Fix offset for Bluetooth enable (BTLE) Test: boot OS (PureOS, Windows 10) on librem13v2, verify BT function key toggle now works correctly. Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/purism/librem/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19897/3 -- To view, visit https://review.coreboot.org/19897 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: elog: Add more wake sources
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19923 ) Change subject: elog: Add more wake sources ...................................................................... elog: Add more wake sources Add wake sources for PME events generated by different devices. BUG=b:37088992 Change-Id: I25098f489f401148171c235cb341f6e7bb2b635b Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/include/elog.h 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/19923/1 diff --git a/src/include/elog.h b/src/include/elog.h index f18aa4b..c11ff2a 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -123,6 +123,28 @@ #define ELOG_WAKE_SOURCE_GPIO 0x04 #define ELOG_WAKE_SOURCE_SMBUS 0x05 #define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_WAKE_SOURCE_PME_HDA 0x07 +#define ELOG_WAKE_SOURCE_PME_GBE 0x08 +#define ELOG_WAKE_SOURCE_PME_EMMC 0x09 +#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a +#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b +#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c +#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d +#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e +#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f +#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10 +#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11 +#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12 +#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13 +#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14 +#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15 +#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16 +#define ELOG_WAKE_SOURCE_PME_SATA 0x17 +#define ELOG_WAKE_SOURCE_PME_CSE 0x18 +#define ELOG_WAKE_SOURCE_PME_CSE2 0x19 +#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a +#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b +#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c struct elog_event_data_wake { u8 source; -- To view, visit https://review.coreboot.org/19923 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I25098f489f401148171c235cb341f6e7bb2b635b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Add detailed information about PME wake s...
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19925 ) Change subject: soc/intel/skylake: Add detailed information about PME wake sources ...................................................................... soc/intel/skylake: Add detailed information about PME wake sources Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/elog.c 1 file changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/19925/1 diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 6db15f5..213b81a 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -17,8 +17,10 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> +#include <device/pci_ops.h> #include <stdint.h> #include <elog.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> @@ -32,6 +34,61 @@ if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); } +} + +struct pme_status_info { + device_t dev; + uint8_t reg_offset; + uint32_t elog_event; +}; + +#define PME_STS_BIT (1 << 15) + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; + device_t dev; + uint16_t val; + bool dev_found = false; + + struct pme_status_info pme_status_info[] = { + {PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA}, + {PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE}, + {PCH_DEV_EMMC, 0x84, ELOG_WAKE_SOURCE_PME_EMMC}, + {PCH_DEV_SDCARD, 0x84, ELOG_WAKE_SOURCE_PME_SDCARD}, + {PCH_DEV_PCIE1, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE1}, + {PCH_DEV_PCIE2, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE2}, + {PCH_DEV_PCIE3, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE3}, + {PCH_DEV_PCIE4, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE4}, + {PCH_DEV_PCIE5, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE5}, + {PCH_DEV_PCIE6, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE6}, + {PCH_DEV_PCIE7, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE7}, + {PCH_DEV_PCIE8, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE8}, + {PCH_DEV_PCIE9, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE9}, + {PCH_DEV_PCIE10, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE10}, + {PCH_DEV_PCIE11, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE11}, + {PCH_DEV_PCIE12, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE12}, + {PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA}, + {PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE}, + {PCH_DEV_CSE_2, 0x54, ELOG_WAKE_SOURCE_PME_CSE2}, + {PCH_DEV_CSE_3, 0x54, ELOG_WAKE_SOURCE_PME_CSE3}, + {PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI}, + {PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI}, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = pme_status_info[i].dev; + val = pci_read_config16(dev, pme_status_info[i].reg_offset); + + if ((val == 0xFFFF) || !(val & PME_STS_BIT)) + continue; + + elog_add_event_wake(pme_status_info[i].elog_event, 0); + dev_found = true; + } + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } static void pch_log_wake_source(struct chipset_power_state *ps) @@ -54,7 +111,7 @@ /* Internal PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) -- To view, visit https://review.coreboot.org/19925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions
by Furquan Shaikh (Code Review) 26 May '17

26 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19924 ) Change subject: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions ...................................................................... soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions This is required to add wake sources for PCIE PME events. BUG=b:37088992 Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/include/soc/pci_devs.h 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/19924/1 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index f51691c..9b86917 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -111,12 +111,18 @@ #define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) #define PCH_DEV_SLOT_PCIE_1 0x1d #define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) #define PCH_DEV_SLOT_STORAGE 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0) -- To view, visit https://review.coreboot.org/19924 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: Documentation: Describe libgfxinit hook-up
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19054 ) Change subject: Documentation: Describe libgfxinit hook-up ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10148/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54425/ : SUCCESS -- To view, visit https://review.coreboot.org/19054 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ieeb53a1694193cd19b5e9aa5bee25e36a60e56bd Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [RFC] util/hugo: Add pre-processing
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19922 ) Change subject: [RFC] util/hugo: Add pre-processing ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10147/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54424/ : SUCCESS -- To view, visit https://review.coreboot.org/19922 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8bb9365e84348997b04ef027b25e316fdac1ad5d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: avoid potential unaligned pointer usage
by build bot (Jenkins) (Code Review) 26 May '17

26 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19921 ) Change subject: ifdtool: avoid potential unaligned pointer usage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10146/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54423/ : SUCCESS -- To view, visit https://review.coreboot.org/19921 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifb2f260c3363ab0f5b4a59e5a4e0b5ecf049fa96 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)tinkermill.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by Arthur Heymans (Code Review) 26 May '17

26 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19143 ) Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/#/c/19143/16/src/northbridge/intel/x4x/raminit.c File src/northbridge/intel/x4x/raminit.c: Line 256: u8 dimm_mask = 0; > thx, not sure if it properly returns failure but I'll definitly check it ou does not work sadly... -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 18 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017