coreboot-gerrit May 2017

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Change in coreboot[master]: mainboard/google/poppy: Enable H1 I2C TPM
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19519 to look at the new patch set (#2). Change subject: mainboard/google/poppy: Enable H1 I2C TPM ...................................................................... mainboard/google/poppy: Enable H1 I2C TPM BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19519/2 -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: mainboard/google/poppy: Enable H1 I2C TPM
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19519 ) Change subject: mainboard/google/poppy: Enable H1 I2C TPM ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53050/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/8892/ : SUCCESS -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/poppy: Enable H1 I2C TPM
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19519 ) Change subject: mainboard/google/poppy: Enable H1 I2C TPM ...................................................................... mainboard/google/poppy: Enable H1 I2C TPM BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19519/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 9aea338..0b5220b 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 select NO_FADT_8042 + select POPPY_USE_I2C_TPM select SOC_INTEL_KABYLAKE if BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4e3ffaf..39739e8 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -213,7 +213,13 @@ device i2c 4b on end end end # I2C #0 - device pci 15.1 on end # I2C #1 + device pci 15.1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device i2c 50 on end + end + end # I2C #1 device pci 15.2 on chip drivers/intel/mipi_camera register "acpi_hid" = ""INT3472"" -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/poppy: Update GPIO table for next build
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19517 ) Change subject: mainboard/google/poppy: Update GPIO table for next build ...................................................................... mainboard/google/poppy: Update GPIO table for next build Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/gpio.c 1 file changed, 25 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19517/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 4d77f5e..fcbbb1d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ PAD_CFG_NC(GPP_A6), - /* A7 : PIRQA# ==> NC */ + /* A7 : PIRQA# ==> NC(TP29) */ PAD_CFG_NC(GPP_A7), /* A8 : CLKRUN# ==> NC(TP45) */ PAD_CFG_NC(GPP_A8), @@ -40,8 +40,8 @@ PAD_CFG_NC(GPP_A11), /* A12 : BM_BUSY# ==> NC */ PAD_CFG_NC(GPP_A12), - /* A13 : SUSWARN# ==> NC */ - PAD_CFG_NC(GPP_A13), + /* A13 : SUSWARN# ==> SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), @@ -130,11 +130,11 @@ /* C8 : UART0_RXD ==> FP_INT */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* C9 : UART0_TXD ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ - /* C10 : UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_C10), - /* C11 : UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_C11), + PAD_CFG_GPO(GPP_C9, 0, DEEP), + /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -147,9 +147,9 @@ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* C18 : I2C1_SDA ==> PCH_I2C1_NFC_3V3_SDA */ + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : I2C1_SCL ==> PCH_I2C1_NFC_3V3_SCL */ + /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -190,8 +190,8 @@ PAD_CFG_NC(GPP_D13), /* D14 : ISH_UART0_TXD ==> NC */ PAD_CFG_NC(GPP_D14), - /* D15 : ISH_UART0_RTS# ==> MIC_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), /* D16 : ISH_UART0_CTS# ==> NC */ PAD_CFG_NC(GPP_D16), /* D17 : DMIC_CLK1 */ @@ -217,14 +217,14 @@ PAD_CFG_NC(GPP_E2), /* E3 : CPU_GP0 ==> NC */ PAD_CFG_NC(GPP_E3), - /* E4 : SATA_DEVSLP0 ==> NFC_RESET_ODL */ - PAD_CFG_GPO(GPP_E4, 0, DEEP), - /* E5 : SATA_DEVSLP1 ==> NFC_INT_L */ - PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), - /* E6 : SATA_DEVSLP2 ==> NFC_FW_DL */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */ + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_CFG_NC(GPP_E4), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC */ + PAD_CFG_NC(GPP_E6), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ PAD_CFG_NC(GPP_E8), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ @@ -346,7 +346,7 @@ /* GPD9: SLP_WLAN# ==> NC(TP25) */ PAD_CFG_NC(GPD9), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), /* TP15 */ + PAD_CFG_NC(GPD10), /* GPD11: LANPHYC ==> NC */ PAD_CFG_NC(GPD11), }; @@ -362,6 +362,11 @@ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/19517 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/poppy: Add support for cr50 I2C TPM
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19518 ) Change subject: mainboard/google/poppy: Add support for cr50 I2C TPM ...................................................................... mainboard/google/poppy: Add support for cr50 I2C TPM 1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/gpio.c 3 files changed, 47 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19518/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index ce32081..9aea338 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -22,6 +22,12 @@ string default "variants/baseboard/devicetree.cb" +config DRIVER_TPM_I2C_BUS + default 0x1 + +config DRIVER_TPM_I2C_ADDR + default 0x50 + config DRIVER_TPM_SPI_BUS default 0x1 @@ -56,6 +62,14 @@ int default 8 +# Select this option to enable use of cr50 I2C TPM on poppy. +config POPPY_USE_I2C_TPM + bool + default n + select I2C_TPM + select MAINBOARD_HAS_I2C_TPM_CR50 + select TPM2 + # Select this option to enable use of cr50 SPI TPM on poppy. # This option is disabled by default. config POPPY_USE_SPI_TPM @@ -64,6 +78,10 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select SPI_TPM select TPM2 + +config TPM_TIS_ACPI_INTERRUPT + int + default 64 # GPE0_DW2_00 (GPP_E0) config VARIANT_DIR string @@ -75,12 +93,5 @@ select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH - -config DRIVER_TPM_SPI_BUS - default 0x1 - -config TPM_TIS_ACPI_INTERRUPT - int - default 64 # GPE0_DW2_00 (GPP_E0) endif # BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d232028..4e3ffaf 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -154,7 +154,7 @@ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen - register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # H1 register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera @@ -167,6 +167,12 @@ .early_init = 1, }" + # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR + # for TPM communication before memory is up. + register "i2c[1]" = "{ + .early_init = 1, + }" + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index fcbbb1d..2be9d0f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -92,6 +92,7 @@ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ PAD_CFG_NC(GPP_B14), +#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -100,6 +101,16 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#else + /* B15 : GSPI0_CS# ==> NC */ + PAD_CFG_NC(GPP_B15), + /* B16 : GSPI0_CLK ==> NC */ + PAD_CFG_NC(GPP_B16), + /* B17 : GSPI0_MISO ==> NC */ + PAD_CFG_NC(GPP_B17), + /* B18 : GSPI0_MOSI ==> NC */ + PAD_CFG_NC(GPP_B18), +#endif /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ @@ -147,10 +158,17 @@ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#else + /* C18 : I2C1_SDA ==> NC */ + PAD_CFG_NC(GPP_C18), + /* C19 : I2C1_SCL ==> NC */ + PAD_CFG_NC(GPP_C19), +#endif /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -353,6 +371,7 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -361,11 +380,14 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#endif +#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +#endif /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ -- To view, visit https://review.coreboot.org/19518 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3...
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19516 ) Change subject: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770K ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53047/ : SUCCESS -- To view, visit https://review.coreboot.org/19516 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Omar Pakker Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3...
by Omar Pakker (Code Review) 02 May '17

02 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19516 to look at the new patch set (#2). Change subject: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770K ...................................................................... util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770K This adds one of the Xeon labeled PCI IDs used in Sandy-/Ivybridge generation processors. This ID is used by the non-Xeon i7 3770K. Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0 Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> --- M util/autoport/sandybridge.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/19516/2 -- To view, visit https://review.coreboot.org/19516 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Omar Pakker Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: nb/intel/x4x/raminit: Remove very long delay
by Arthur Heymans (Code Review) 02 May '17

02 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19514 ) Change subject: nb/intel/x4x/raminit: Remove very long delay ...................................................................... Patch Set 2: It could just come from SerialICE being very slow here or something like that? anyway 250ms is extremely long... -- To view, visit https://review.coreboot.org/19514 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/gm45: Set display backlight according to EDID string
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19500 ) Change subject: nb/intel/gm45: Set display backlight according to EDID string ...................................................................... Patch Set 13: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53045/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8888/ : SUCCESS -- To view, visit https://review.coreboot.org/19500 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843 Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3...
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19516 ) Change subject: util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770K ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53046/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/8889/ : SUCCESS -- To view, visit https://review.coreboot.org/19516 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Omar Pakker Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit May 2017