Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18917
to look at the new patch set (#18).
Change subject: soc/intel/common/block:[WIP] Add GPIO common code
......................................................................
soc/intel/common/block:[WIP] Add GPIO common code
Here are some differences between APL and SKL GPIO registers
DW0:
PMODE: SKL[11:10] and APL[12:10]
RXTXENCFG: APL[21:20] and RSVD in SKL
PREGFRXSEL: APL[24]…
[View More] and RSVD in SKL
DW1: SKL only has INTSEL and TERM whereas APL and GLK share same bit
definitions for rest of the bits that are reserved in SKL
EVMAP and EVOUTEN are not there on SKL
DW1_PAD_TOL has been used only in SKL
Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
A src/soc/intel/common/block/gpio/Kconfig
A src/soc/intel/common/block/gpio/Makefile.inc
A src/soc/intel/common/block/gpio/gpio.c
A src/soc/intel/common/block/include/intelblocks/gpio.h
A src/soc/intel/common/block/include/intelblocks/gpio_defs.h
5 files changed, 807 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/18917/18
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Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Gerrit-PatchSet: 18
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com>
Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com>
Gerrit-Reviewer: Dhaval Sharma <dhaval.v.sharma(a)intel.com>
Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>
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Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>
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Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
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Martin Roth has uploaded a new change for review. ( https://review.coreboot.org/19601 )
Change subject: intel/common/block: Fix incorrect defines
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intel/common/block: Fix incorrect defines
These #defines were part of a patch train where they were changed from
...APOLLOLAKE... to ...APL... Unfortunately, the follow-on commits
in the train were not updated or rebased, so this issue wasn't caught
until they were merged.
…
[View More]Change-Id: I711f96e1d6c88ec207b29898a747337beee87c50
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/xhci/xhci.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19601/1
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 272fe7a..f05d9f4 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -471,7 +471,7 @@
.ops = &cse_ops,
.vendor = PCI_VENDOR_ID_INTEL,
/* SoC/chipset needs to provide PCI device ID */
- .device = PCI_DEVICE_ID_INTEL_APOLLOLAKE_CSE0
+ .device = PCI_DEVICE_ID_INTEL_APL_CSE0
};
#endif
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index d1f7579..50fe1de 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -30,7 +30,7 @@
};
static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_INTEL_APOLLOLAKE_XHCI,
+ PCI_DEVICE_ID_INTEL_APL_XHCI,
PCI_DEVICE_ID_INTEL_GLK_XHCI,
PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
--
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Gerrit-Change-Id: I711f96e1d6c88ec207b29898a747337beee87c50
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Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19593 )
Change subject: inteltool: Add dumping of full PCR ports
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Patch Set 1:
(3 comments)
I didn't finish reviewing this but I thought better to post it now than wait until after the weekend.
https://review.coreboot.org/#/c/19593/1/util/inteltool/Makefile
File util/inteltool/Makefile:
Line 25: CFLAGS ?= -O2 -g -Wall -W -I$(top)/src/…
[View More]commonlib/include -Wextra -pedantic
Any specific reason you're adding these flags ? And shouldn't they be added on their own commit ?
https://review.coreboot.org/#/c/19593/1/util/inteltool/pcr.c
File util/inteltool/pcr.c:
Line 114: printf("P2SB Control = 0x%08"PRIx32"\n", pci_read_long(p2sb, 0xe0));
Sould this even be in the pcr_init ? I think it belongs in its own print_pcr_endpoints_info function.
Line 132: endpoint_mask & ~(1 << j));
This looks like it enables an endpoint to see if it's locked or not. But it doesn't restore it back to how it was.
Also, the 'endpoint_mask == pci_read_long' check will fail for the other 31 endpoints as soon as the first endpoint is not locked.
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Gerrit-Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
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