Hello Arthur Heymans, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18011
to look at the new patch set (#9).
Change subject: mainboard/lenovo/t430: Add Thinkpad T430 support
......................................................................
mainboard/lenovo/t430: Add Thinkpad T430 support
Tested and working:
* HDD LED
* Booting GNU Linux 4.9 from HDD using SeaBios
* Booting GNU Linux 4.9 from USB using SeaBios
* Native GFX init
* All Fn function keys
* Speakers
* PCIe Wifi
* Camera
* WWAN
* Fan (Dynamic Thermal Managment)
* Flashing using internal programmer
* Dual memory DIMMs running at up to DDR3-1866
* AC events
* Touchpad, trackball and keyboard
* USB3 ports running at SuperSpeed
* Ethernet
* Headphone jack
* Speaker mute
* Microphone mute
* Volume keys
* Fingerprint sensor
* Lid switch
* Thinklight
* TPM (disable SeaBios CONFIG_TCGBIOS)
* CMOS options:
** power_on_after_fail
** reboot_counter
** boot_option
** gfx_uma_size
Untested:
* Booting Windows
* Hybrid graphics
* Docking station
* VGA
Broken:
* Wifi LED is always on
Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
A src/mainboard/lenovo/t430/Kconfig
A src/mainboard/lenovo/t430/Kconfig.name
A src/mainboard/lenovo/t430/Makefile.inc
A src/mainboard/lenovo/t430/acpi/ec.asl
A src/mainboard/lenovo/t430/acpi/platform.asl
A src/mainboard/lenovo/t430/acpi/superio.asl
A src/mainboard/lenovo/t430/acpi_tables.c
A src/mainboard/lenovo/t430/board_info.txt
A src/mainboard/lenovo/t430/cmos.default
A src/mainboard/lenovo/t430/cmos.layout
A src/mainboard/lenovo/t430/devicetree.cb
A src/mainboard/lenovo/t430/dsdt.asl
A src/mainboard/lenovo/t430/gpio.c
A src/mainboard/lenovo/t430/hda_verb.c
A src/mainboard/lenovo/t430/mainboard.c
A src/mainboard/lenovo/t430/romstage.c
A src/mainboard/lenovo/t430/smihandler.c
A src/mainboard/lenovo/t430/thermal.h
18 files changed, 1,075 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/18011/9
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Gerrit-PatchSet: 9
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/18011 )
Change subject: mainboard/lenovo/t430: Add Thinkpad T430 support
......................................................................
Patch Set 8:
(16 comments)
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/cmos.layo…
File src/mainboard/lenovo/t430/cmos.layout:
Line 51: 392 3 e 5 baud_rate
> For what?
OK
Line 59: 409 2 e 7 power_on_after_fail
> Does this option work correctly? Sometimes the EC controls it, but
Tested and working
Line 75: 424 1 e 2 hyper_threading
> Beside the hype around this option, I still doubt it did something
OK
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/devicetre…
File src/mainboard/lenovo/t430/devicetree.cb:
PS8, Line 3: 0x80000410, 0x00000005
> Why specify more than 3 values if ndid is 3?
OK
PS8, Line 18: 0x11551155
> IIRC, "gpu_cpu_backlight" is in charge. If in doubt, keep the lower
OK
PS8, Line 41: # Intel Series 6 Cougar Point PCH
> The comment is dubious. T430 should have a Panther Point PCH.
OK
Line 46: register "gen3_dec" = "0x00000000"
> 0 is the default.
OK
Line 47: register "gen4_dec" = "0x000c06a1"
> Why use gen1, gen2, gen4 instead of gen1, gen2, gen3?
PMH7, not sure about the other one
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/dsdt.asl
File src/mainboard/lenovo/t430/dsdt.asl:
PS8, Line 18: #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
: #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
: #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
: #define EC_LENOVO_H8_ME_WORKAROUND 1
: #define THINKPAD_EC_GPE 17
> `acpi/ec.asl` would be a better place, IMO.
OK
PS8, Line 43: #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
: #include <southbridge/intel/bd82x6x/acpi/pch.asl>
: #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
> indent one more level?
OK
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/gpio.c
File src/mainboard/lenovo/t430/gpio.c:
Line 17: const struct pch_gpio_set1 pch_gpio_set1_mode = {
> empty line between header?
OK
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/hda_verb.c
File src/mainboard/lenovo/t430/hda_verb.c:
PS8, Line 22: 0x0000000b
> A decimal 11 would be much more readable.
OK
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/romstage.c
File src/mainboard/lenovo/t430/romstage.c:
PS8, Line 26: CNF2_LPC_EN | CNF1_LPC_EN
> What for?
TPM
PS8, Line 29: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
: pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
: pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
> Are these all needed before the devicetree values kick in?
No
Line 35: pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
> Why? Possible side effects with early_me code?
Yes, side effects are possible
https://review.coreboot.org/#/c/18011/8/src/mainboard/lenovo/t430/thermal.h
File src/mainboard/lenovo/t430/thermal.h:
PS8, Line 21:
> tabs ?
OK
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Gerrit-MessageType: comment
Gerrit-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630
Gerrit-PatchSet: 8
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19571 )
Change subject: mb/lenovo/*/romstage: Remove COM IO port
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/19571/1/src/mainboard/lenovo/l520/romstage.c
File src/mainboard/lenovo/l520/romstage.c:
Line 28: pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);
> Does this leave COMB_LPC_EN set, which after change of register 0x80 routes
maybe use macros defined for both values and register offsets?
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
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Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/19671 )
Change subject: drivers/storage: Delay after SD SWITCH operations
......................................................................
drivers/storage: Delay after SD SWITCH operations
Delay for a while after the switch operations to let the card recover.
TEST=Build and run on Galileo Gen2
Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05
Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
Reviewed-on: https://review.coreboot.org/19671
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/drivers/storage/sd.c
1 file changed, 13 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/src/drivers/storage/sd.c b/src/drivers/storage/sd.c
index 18d2c0e..6f4887a 100644
--- a/src/drivers/storage/sd.c
+++ b/src/drivers/storage/sd.c
@@ -136,6 +136,7 @@
int sd_change_freq(struct storage_media *media)
{
+ int delay;
int err, timeout;
struct mmc_command cmd;
struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
@@ -225,11 +226,23 @@
if (!((ctrlr->caps & DRVR_CAP_HS52) && (ctrlr->caps & DRVR_CAP_HS)))
goto out;
+ /* Give the card time to recover afer the switch operation. Wait for
+ * 9 (>= 8) clock cycles receiving the switch status.
+ */
+ delay = (9000000 + ctrlr->bus_hz - 1) / ctrlr->bus_hz;
+ udelay(delay);
+
+ /* Switch to high speed */
err = sd_switch(ctrlr, SD_SWITCH_SWITCH, 0, 1,
(uint8_t *)switch_status);
if (err)
return err;
+ /* Give the card time to perform the switch operation. Wait for 9
+ * (>= 8) clock cycles receiving the switch status.
+ */
+ udelay(delay);
+
if ((ntohl(switch_status[4]) & 0x0f000000) == 0x01000000) {
media->caps |= DRVR_CAP_HS;
SET_TIMING(ctrlr, BUS_TIMING_SD_HS);
--
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Change subject: xcompile: silence clang when referencing packed structs' members
......................................................................
Patch Set 1:
> > cross memory map boundaries), however armv4 and mips do care. I
> > don't know about riscv/power. That's why I wonder where clang
> > reported this warning. Maybe it worths disabling it checking
> > $SUBARCH not matching arm-armv4 and mips*-mips?
>
> x86, armv7, armv8. memory map boundaries would be indicative of a
> larger problem given that we're looking at fields within a data
> structure.
Yeah :) So should I understand Clang complains only appear in x86, armv7, armv8?
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Change subject: arch/arm64: Use variables of the right size for msr/mrs opcodes
......................................................................
Patch Set 1: -Code-Review
> As for using uint64_t, that would be wrong: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488d/ch09s0… specifies cntfrq_el0 to be 32 bit wide.
Ok!
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/19659 )
Change subject: xcompile: silence clang when referencing packed structs' members
......................................................................
Patch Set 1:
> > multiple locations, and it's bogus everywhere: if we use packed
> > structs, it's because we expect a certain memory layout (and I
> > know, modern C compilers needn't adhere to any reasonable
> > interpretation of that). If we refer to any such element, it
> might
> > not be aligned, we know, we don't care.
>
> I agree x86 and armv7 don't care (on armv7 as long as it does not
> cross memory map boundaries), however armv4 and mips do care. I
> don't know about riscv/power. That's why I wonder where clang
> reported this warning. Maybe it worths disabling it checking
> $SUBARCH not matching arm-armv4 and mips*-mips?
x86, armv7, armv8. memory map boundaries would be indicative of a larger problem given that we're looking at fields within a data structure.
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