Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18917
to look at the new patch set (#23).
Change subject: soc/intel/common/block:[WIP] Add GPIO common code
......................................................................
soc/intel/common/block:[WIP] Add GPIO common code
Here are some differences between APL and SKL GPIO registers
DW0:
PMODE: SKL[11:10] and APL[12:10]
RXTXENCFG: APL[21:20] and RSVD in SKL
PREGFRXSEL: APL[24] and RSVD in SKL
DW1: SKL only has INTSEL and TERM whereas APL and GLK share same bit
definitions for rest of the bits that are reserved in SKL
(e.g. IoStandby state and term)
EVMAP and EVOUTEN are not there on SKL
DW1_PAD_TOL has been used only in SKL
Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
A src/soc/intel/common/block/gpio/Kconfig
A src/soc/intel/common/block/gpio/Makefile.inc
A src/soc/intel/common/block/gpio/gpio.c
A src/soc/intel/common/block/include/intelblocks/gpio.h
A src/soc/intel/common/block/include/intelblocks/gpio_defs.h
5 files changed, 842 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/18917/23
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c
Gerrit-PatchSet: 23
Gerrit-Project: coreboot
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19661 )
Change subject: arch/arm64: Use variables of the right size for msr/mrs opcodes
......................................................................
Patch Set 1: Code-Review+2
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Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19690 )
Change subject: src/southbridge/i82801gx: Include a default SeaBIOS config file
......................................................................
src/southbridge/i82801gx: Include a default SeaBIOS config file
Some ICH7 variants do not feature AHCI which will result in SeaBIOS
Port Mapped I/O for disk access which is quite slow. Using DMA results
in much faster disk operations.
Change-Id: I6a6e79ea6cd0a14070b8092aefa477b9e3a0c4b1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/intel/i82801gx/Kconfig
A src/southbridge/intel/i82801gx/config_seabios
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19690/1
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index b2265c4..003cdac 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -39,4 +39,12 @@
hex
default 0x80
+config PAYLOAD_CONFIGFILE
+ string
+ default "$(top)/src/southbridge/intel/i82801gx/config_seabios" if PAYLOAD_SEABIOS
+ help
+ Some ICH7 variants do not have AHCI on which SeaBIOS will use
+ Port Mapped I/O for disk access by default. Using DMA will result
+ in much faster disk operations.
+
endif
diff --git a/src/southbridge/intel/i82801gx/config_seabios b/src/southbridge/intel/i82801gx/config_seabios
new file mode 100644
index 0000000..76d48ed
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/config_seabios
@@ -0,0 +1 @@
+CONFIG_ATA_DMA=y
\ No newline at end of file
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19126 )
Change subject: util/release: Update build-release script
......................................................................
Patch Set 2: Code-Review+2
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