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Change in coreboot[master]: arch/arm: Correct checkpatch errors
by Logan Carlson (Code Review) 31 May '17

31 May '17

Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19989 ) Change subject: arch/arm: Correct checkpatch errors ...................................................................... arch/arm: Correct checkpatch errors Correct whitespace issues in arch/arm and arch/arm64. Enclose complex values in parenthesis. Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Signed-off-by: Logan Carlson <logancarlson(a)google.com> --- M src/arch/arm/div0.c M src/arch/arm/eabi_compat.c M src/arch/arm/include/armv4/arch/smp/spinlock.h M src/arch/arm/include/armv7.h M src/arch/arm/include/smp/spinlock.h M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/lib/cache.c 7 files changed, 25 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/19989/1 diff --git a/src/arch/arm/div0.c b/src/arch/arm/div0.c index afd9dad..e474f73 100644 --- a/src/arch/arm/div0.c +++ b/src/arch/arm/div0.c @@ -19,7 +19,7 @@ /* Replacement (=dummy) for GNU/Linux division-by zero handler */ /* recursion is ok here because we have no formats ... */ -void __div0 (void) +void __div0(void) { printk(BIOS_EMERG, "DIVIDE BY ZERO! continuing ...\n"); } diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index e49f199..15f7d36 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -20,8 +20,8 @@ #include <console/console.h> /* FIXME(dhendrix): prototypes added for assembler */ -int raise (int signum) __attribute__((used)); -int raise (int signum) +int raise(int signum) __attribute__((used)); +int raise(int signum) { printk(BIOS_CRIT, "raise: Signal # %d caught\n", signum); return 0; diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h index 6c5f6e8..e49dc44 100644 --- a/src/arch/arm/include/armv4/arch/smp/spinlock.h +++ b/src/arch/arm/include/armv4/arch/smp/spinlock.h @@ -15,12 +15,12 @@ #define _ARCH_SMP_SPINLOCK_H #define DECLARE_SPIN_LOCK(x) -#define barrier() do {} while(0) +#define barrier() do {} while (0) #define spin_is_locked(lock) 0 -#define spin_unlock_wait(lock) do {} while(0) -#define spin_lock(lock) do {} while(0) -#define spin_unlock(lock) do {} while(0) -#define cpu_relax() do {} while(0) +#define spin_unlock_wait(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define cpu_relax() do {} while (0) #include <smp/node.h> #define boot_cpu() 1 diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index 6622a6f..bec7fd7 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -54,8 +54,8 @@ * However, we use the CP15 based instructions because we use * -march=armv5 in U-Boot */ -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) +#define CP15ISB (asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))) +#define CP15DSB (asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))) +#define CP15DMB (asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))) #endif /* ARMV7_H */ diff --git a/src/arch/arm/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h index a8f9c77..f98900a 100644 --- a/src/arch/arm/include/smp/spinlock.h +++ b/src/arch/arm/include/smp/spinlock.h @@ -29,9 +29,9 @@ #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; -#define barrier() __asm__ __volatile__("": : :"memory") +#define barrier() (__asm__ __volatile__("" : : : "memory")) #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) != 0) -#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) +#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) static inline __attribute__((always_inline)) void spin_lock(spinlock_t *lock) { diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 4f91de0..68c7df2 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -86,7 +86,7 @@ dsb(); while ((void *)line < addr + len) { - switch(op) { + switch (op) { case OP_DCCIVAC: dccivac(line); break; diff --git a/src/arch/arm64/armv8/lib/cache.c b/src/arch/arm64/armv8/lib/cache.c index b4ecda6..0c621ef 100644 --- a/src/arch/arm64/armv8/lib/cache.c +++ b/src/arch/arm64/armv8/lib/cache.c @@ -23,55 +23,55 @@ void dccisw(uint64_t cisw) { - __asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) :"memory"); + __asm__ __volatile__("dc cisw, %0\n\t" : : "r" (cisw) : "memory"); } void dccivac(uint64_t civac) { - __asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) :"memory"); + __asm__ __volatile__("dc civac, %0\n\t" : : "r" (civac) : "memory"); } void dccsw(uint64_t csw) { - __asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) :"memory"); + __asm__ __volatile__("dc csw, %0\n\t" : : "r" (csw) : "memory"); } void dccvac(uint64_t cvac) { - __asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) :"memory"); + __asm__ __volatile__("dc cvac, %0\n\t" : : "r" (cvac) : "memory"); } void dccvau(uint64_t cvau) { - __asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) :"memory"); + __asm__ __volatile__("dc cvau, %0\n\t" : : "r" (cvau) : "memory"); } void dcisw(uint64_t isw) { - __asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) :"memory"); + __asm__ __volatile__("dc isw, %0\n\t" : : "r" (isw) : "memory"); } void dcivac(uint64_t ivac) { - __asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) :"memory"); + __asm__ __volatile__("dc ivac, %0\n\t" : : "r" (ivac) : "memory"); } void dczva(uint64_t zva) { - __asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) :"memory"); + __asm__ __volatile__("dc zva, %0\n\t" : : "r" (zva) : "memory"); } void iciallu(void) { - __asm__ __volatile__("ic iallu\n\t" : : :"memory"); + __asm__ __volatile__("ic iallu\n\t" : : : "memory"); } void icialluis(void) { - __asm__ __volatile__("ic ialluis\n\t" : : :"memory"); + __asm__ __volatile__("ic ialluis\n\t" : : : "memory"); } void icivau(uint64_t ivau) { - __asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) :"memory"); + __asm__ __volatile__("ic ivau, %0\n\t" : : "r" (ivau) : "memory"); } -- To view, visit https://review.coreboot.org/19989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com>

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Change in coreboot[master]: cpu/amd/car: Fix checkpatch warnings
by Evelyn Huang (Code Review) 31 May '17

31 May '17

Evelyn Huang has uploaded a new change for review. ( https://review.coreboot.org/19988 ) Change subject: cpu/amd/car: Fix checkpatch warnings ...................................................................... cpu/amd/car: Fix checkpatch warnings Fix line over 80 characters warnings and space after function name warning. Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3 Signed-off-by: Evelyn Huang <evhuang(a)google.com> --- M src/cpu/amd/car/disable_cache_as_ram.c M src/cpu/amd/car/post_cache_as_ram.c 2 files changed, 30 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/19988/1 diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index bab464e..efc9118 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -4,7 +4,8 @@ * original idea yhlu 6.2005 (assembler code) * * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +32,8 @@ return family; } -static inline __attribute__((always_inline)) void disable_cache_as_ram(uint8_t skip_sharedc_config) +static inline __attribute__((always_inline)) +void disable_cache_as_ram(uint8_t skip_sharedc_config) { msr_t msr; uint32_t family; @@ -52,12 +54,17 @@ #if CONFIG_DCACHE_RAM_SIZE > 0x18000 wrmsr(MTRR_FIX_4K_D8000, msr); #endif - /* disable fixed mtrr from now on, it will be enabled by ramstage again */ + /* disable fixed mtrr from now on, + * it will be enabled by ramstage again + */ msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn + | SYSCFG_MSR_MtrrFixDramModEn); wrmsr(SYSCFG_MSR, msr); - /* Set the default memory type and disable fixed and enable variable MTRRs */ + /* Set the default memory type and + * disable fixed and enable variable MTRRs + */ msr.hi = 0; msr.lo = (1 << 11); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index efcd111..064222a 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -48,20 +48,23 @@ static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", - (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1)); + (uint32_t) s, (uint32_t) (s + len - 1), + (uint32_t) d, (uint32_t) (d + len - 1)); memcpy(d, s, len); } static void memset_(void *d, int val, size_t len) { - print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); + print_car_debug(" Fill [%08x-%08x] ...", + (uint32_t) d, (uint32_t) (d + len - 1)); memset(d, val, len); } static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", - (uint32_t) s, (uint32_t) (s + len - 1), (uint32_t) d, (uint32_t) (d + len - 1)); + (uint32_t) s, (uint32_t) (s + len - 1), + (uint32_t) d, (uint32_t) (d + len - 1)); return memcmp(d, s, len); } @@ -71,10 +74,13 @@ print_car_debug("Prepare CAR migration and stack regions..."); if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + void *resume_backup_memory = + acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); + memcpy_(resume_backup_memory + + HIGH_MEMORY_SAVE - backup_top, + (void *)(CONFIG_RAMTOP - backup_top), + backup_top); } memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); @@ -87,7 +93,8 @@ print_car_debug("Prepare ramstage memory region..."); if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + void *resume_backup_memory = + acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, HIGH_MEMORY_SAVE - backup_top); @@ -118,7 +125,9 @@ * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE); + lower_stack_boundary = + (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) + - CONFIG_DCACHE_BSP_STACK_SIZE); if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); @@ -159,7 +168,7 @@ /* We do not come back. */ } -void cache_as_ram_new_stack (void) +void cache_as_ram_new_stack(void) { print_car_debug("Disabling cache as RAM now\n"); disable_cache_as_ram_bsp(); -- To view, visit https://review.coreboot.org/19988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com>

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Change in coreboot[master]: src/cpu/amd/quadcore Fix checkpatch errors/warnings
by Evelyn Huang (Code Review) 31 May '17

31 May '17

Evelyn Huang has uploaded a new change for review. ( https://review.coreboot.org/19987 ) Change subject: src/cpu/amd/quadcore Fix checkpatch errors/warnings ...................................................................... src/cpu/amd/quadcore Fix checkpatch errors/warnings Fix over 80 character line warnings, unncessary braces for single statement blocks warnings, include space before and after =, <, > warnings, spaces after open parantheses warnings Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Signed-off-by: Evelyn Huang <evhuang(a)google.com> --- M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/amd/quadcore/quadcore.c M src/cpu/amd/quadcore/quadcore_id.c 3 files changed, 51 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/19987/1 diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index c4eb50c..f72e9ef 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -38,16 +38,15 @@ { device_t dev; u32 nodeid; - u32 siblings=0; + u32 siblings = 0; //get max siblings from all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid = 0; nodeid < nodes; nodeid++) { int j; dev = get_node_pci(nodeid, 3); j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if (siblings < j) { + if (siblings < j) siblings = j; - } } return siblings; @@ -60,7 +59,7 @@ u32 nodeid; //enable APIC_EXIT_ID all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid = 0; nodeid < nodes; nodeid++) { u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); @@ -82,9 +81,11 @@ siblings = get_max_siblings(sysconf.nodes); - if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0 + if (sysconf.bsp_apicid > 0) { + // IOAPIC could start from 0 return 0; - } else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0 + } else if (sysconf.enabled_apic_ext_id) { + // enabled ext id but bsp = 0 return 1; } @@ -93,7 +94,7 @@ //Construct apicid_base - if ((!disable_siblings) && (siblings>0) ) { + if ((!disable_siblings) && (siblings > 0)) { /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make IOAPIC work. I don't @@ -101,14 +102,16 @@ (APIC_EXT_ID is enabled) */ //4:10 for two way 8:12 for four way 16:16 for eight way - //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : 8 * siblings + sysconf.nodes; + //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes + //for better consistency? + apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes : + 8 * siblings + sysconf.nodes; } else { apicid_base = sysconf.nodes; } - if ((apicid_base+ioapic_num-1)>0xf) { + if ((apicid_base+ioapic_num-1) > 0xf) { // We need to enable APIC EXT ID printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n"); enable_apic_ext_id(sysconf.nodes); diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 2f0822e..f29d61e 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -2,7 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, + * Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,9 +35,9 @@ dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) - dword = ((dword & 8) >> 1) | (dword & 3); + dword = ((dword & 8) >> 1) | (dword & 3); else - dword &= 3; + dword &= 3; } return dword; } @@ -57,7 +58,8 @@ ssize_t i; uint32_t dword; - printk(BIOS_DEBUG, "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores); + printk(BIOS_DEBUG, + "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores); /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 */ @@ -72,15 +74,16 @@ uint32_t core_activation_flags = 0; uint32_t active_cores = 0; - /* Set PCI_DEV(0, 0x18+nodeid, 0), 0x1dc bits 7:1 to start cores */ + /* Set PCI_DEV(0, 0x18+nodeid, 0), + * 0x1dc bits 7:1 to start cores + */ dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc); - for (i = 1; i < cores + 1; i++) { + for (i = 1; i < cores + 1; i++) core_activation_flags |= 1 << i; - } - /* Start the first core of each compute unit */ active_cores |= core_activation_flags & 0x55; - pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | active_cores); + pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword + | active_cores); /* Each core shares a single set of MTRR registers with * another core in the same compute unit, therefore, it @@ -93,14 +96,17 @@ uint32_t timeout; for (i = 1; i < cores + 1; i++) { if (!(i & 0x1)) { - uint32_t ap_apicid = get_boot_apic_id(nodeid, i); - timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + uint32_t ap_apicid = + get_boot_apic_id(nodeid, i); + timeout = wait_cpu_state(ap_apicid, + F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); } } /* Start the second core of each compute unit */ active_cores |= core_activation_flags & 0xaa; - pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | active_cores); + pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword | + active_cores); } else { // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1 dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68); @@ -109,9 +115,8 @@ if (cores > 1) { dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168); - for (i = 0; i < cores - 1; i++) { + for (i = 0; i < cores - 1; i++) dword |= 1 << i; - } pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword); } } @@ -134,10 +139,10 @@ for (nodeid = 0; nodeid < nodes; nodeid++) { u32 cores = get_core_num_in_bsp(nodeid); - printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores); - if (cores > 0) { + printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", + nodeid, cores); + if (cores > 0) real_start_other_core(nodeid, cores); - } } } #endif diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index cd83906..97f89ac 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -1,12 +1,13 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, + * Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. +* the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -26,7 +27,7 @@ { msr_t msr; msr = rdmsr(NB_CFG_MSR); - return ( ( msr.hi >> (54-32)) & 1); + return ((msr.hi >> (54-32)) & 1); } u32 get_initial_apicid(void) @@ -75,7 +76,7 @@ * The apicid format varies based on processor revision */ apicid = (cpuid_ebx(1) >> 24) & 0xff; - if ( nb_cfg_54) { + if (nb_cfg_54) { if (fam15h && dual_node) { id.coreid = apicid & 0x1f; id.nodeid = (apicid & 0x60) >> 5; @@ -105,8 +106,10 @@ } } if (fam15h && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. - * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... + /* Coreboot expects each separate processor die to be on a + * different nodeid. + * Since the code above returns nodeid 0 even on + * internal node 1 some fixup is needed... */ uint32_t f5x84; uint8_t core_count; @@ -123,10 +126,13 @@ id.coreid = id.coreid - core_count; } } else if (rev_gte_d && dual_node) { - /* Coreboot expects each separate processor die to be on a different nodeid. - * Since the code above returns nodeid 0 even on internal node 1 some fixup is needed... + /* Coreboot expects each separate processor die to be on a + * different nodeid. + * Since the code above returns nodeid 0 even on + * internal node 1 some fixup is needed... */ - uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | ((f3xe8 & 0x00003000) >> 12)) + 1; + uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) | + ((f3xe8 & 0x00003000) >> 12)) + 1; id.nodeid = id.nodeid * 2; if (id.coreid >= core_count) { -- To view, visit https://review.coreboot.org/19987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com>

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Change in coreboot[master]: google/kahlee: Enable TPM
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19848 ) Change subject: google/kahlee: Enable TPM ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10306/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54592/ : SUCCESS -- To view, visit https://review.coreboot.org/19848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Save VBNV data to CMOS
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19847 ) Change subject: google/kahlee: Save VBNV data to CMOS ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10305/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54591/ : SUCCESS -- To view, visit https://review.coreboot.org/19847 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd: Fix most checkpatch errors
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19986 ) Change subject: soc/amd: Fix most checkpatch errors ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54593/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10307/ : SUCCESS -- To view, visit https://review.coreboot.org/19986 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Add Realtek audio codec ASL
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19845 ) Change subject: google/kahlee: Add Realtek audio codec ASL ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10303/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54589/ : SUCCESS -- To view, visit https://review.coreboot.org/19845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Set DDI port 2 to DP
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19846 ) Change subject: google/kahlee: Set DDI port 2 to DP ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10304/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54590/ : SUCCESS -- To view, visit https://review.coreboot.org/19846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Fix ASL whitespace and formatting
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19843 ) Change subject: google/kahlee: Fix ASL whitespace and formatting ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10301/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54587/ : SUCCESS -- To view, visit https://review.coreboot.org/19843 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Enable verstage support
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19756 ) Change subject: soc/amd/stoneyridge: Enable verstage support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10287/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54572/ : SUCCESS -- To view, visit https://review.coreboot.org/19756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017