coreboot-gerrit May 2017

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Change in coreboot[master]: cpu/amd/car: Fix checkpatch warnings
by Philippe Mathieu-Daudé (Code Review) 31 May '17

31 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19988 ) Change subject: cpu/amd/car: Fix checkpatch warnings ...................................................................... Patch Set 1: Code-Review+1 (4 comments) https://review.coreboot.org/#/c/19988/1/src/cpu/amd/car/disable_cache_as_ra… File src/cpu/amd/car/disable_cache_as_ram.c: PS1, Line 61: msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn : | SYSCFG_MSR_MtrrFixDramModEn); too bad this doesn't fit in one line https://review.coreboot.org/#/c/19988/1/src/cpu/amd/car/post_cache_as_ram.c File src/cpu/amd/car/post_cache_as_ram.c: PS1, Line 51: what about those spaces between type cast and value? PS1, Line 51: here too PS1, Line 67: until here -- To view, visit https://review.coreboot.org/19988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Philippe Mathieu-Daudé (Code Review) 31 May '17

31 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc: Add AMD Stoney Ridge southbridge code
by Marc Jones (Code Review) 31 May '17

31 May '17

Marc Jones has posted comments on this change. ( https://review.coreboot.org/19722 ) Change subject: soc: Add AMD Stoney Ridge southbridge code ...................................................................... Patch Set 4: created the following issues to track problems found in review: Kahlee: coreboot - stoneyridge - check uart index bounds 62201567 Kahlee: coreboot - stoneyridge - use device macros 62200746 Kahlee: coreboot -stoneyridge - fix lpc.c 62200877 Kahlee: coreboot -- stoneyridge - fix and find the correct location for amd_pci_int_types.h 62200834 Kahlee: coreboot - stoneyridge - find the correct location for amd_pci_int_defs.h 62200907 Kahlee: coreboot -stoneyridge - fix guarded code 62200858 Kahlee: coreboot - stoneyridge - clean up hudson.c 62200891 Kahlee: coreboot - stoneyridge - rename hudson.c and hudson.h 62200157 Kahlee: coreboot - stoneyridge - cleanup sd.c 62200312 Kahlee: coreboot - stoneyridge - fix sata.c 62200375 Kahlee: coreboot - clean up stoneyridge smbus files 62200225 Kahlee: coreboot - cleanup magic southbridge registers 62199625 Kahlee: coreboot soc cleanup - remove unused and non NULL function pointers and empty functions 62199225 -- To view, visit https://review.coreboot.org/19722 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch/arm: Correct checkpatch errors
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19989 ) Change subject: arch/arm: Correct checkpatch errors ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10310/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54596/ : SUCCESS -- To view, visit https://review.coreboot.org/19989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch/arm/include/armv7/arch: Correct keyword organization in...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19991 ) Change subject: arch/arm/include/armv7/arch: Correct keyword organization in cpu.h ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10312/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54598/ : SUCCESS -- To view, visit https://review.coreboot.org/19991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/cpu/amd/quadcore Fix checkpatch errors/warnings
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19987 ) Change subject: src/cpu/amd/quadcore Fix checkpatch errors/warnings ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10308/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54594/ : SUCCESS -- To view, visit https://review.coreboot.org/19987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/car: Fix checkpatch warnings
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19988 ) Change subject: cpu/amd/car: Fix checkpatch warnings ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10309/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54595/ : SUCCESS -- To view, visit https://review.coreboot.org/19988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/quadcore: Correct checkpatch errors
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19990 ) Change subject: cpu/amd/quadcore: Correct checkpatch errors ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10311/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54597/ : SUCCESS -- To view, visit https://review.coreboot.org/19990 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idc48d1177db474649cddd8a2f496e330eaabb113 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch/arm/include/armv7/arch: Correct keyword organization in...
by Logan Carlson (Code Review) 31 May '17

31 May '17

Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19991 ) Change subject: arch/arm/include/armv7/arch: Correct keyword organization in cpu.h ...................................................................... arch/arm/include/armv7/arch: Correct keyword organization in cpu.h Move the inline keyword in between the static keyword and the return type. Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Signed-off-by: Logan Carlson <logancarlson(a)google.com> --- M src/arch/arm/include/armv7/arch/cpu.h 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/19991/1 diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index d70622f..b87e3c8 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -49,7 +49,7 @@ /* Primitives for CPU and MP cores. */ /* read Main Id register (MIDR) */ -inline static uint32_t read_midr(void) +static inline uint32_t read_midr(void) { uint32_t value; asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value)); @@ -57,7 +57,7 @@ } /* read Multiprocessor Affinity Register (MPIDR) */ -inline static uint32_t read_mpidr(void) +static inline uint32_t read_mpidr(void) { uint32_t value; asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value)); @@ -65,7 +65,7 @@ } /* read Auxiliary Control Register (ACTLR) */ -inline static uint32_t read_actlr(void) +static inline uint32_t read_actlr(void) { uint32_t val = 0; asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val)); @@ -73,25 +73,25 @@ } /* write Auxiliary Control Register (ACTLR) */ -inline static void write_actlr(uint32_t val) +static inline void write_actlr(uint32_t val) { asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val)); } /* wait for interrupt. */ -inline static void wfi(void) +static inline void wfi(void) { asm volatile ("wfi" : : : "memory"); } /* wait for event. */ -inline static void wfe(void) +static inline void wfe(void) { asm volatile ("wfe"); } /* set event (to bring up cores in WFE state). */ -inline static void sev(void) +static inline void sev(void) { asm volatile ("sev"); } -- To view, visit https://review.coreboot.org/19991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com>

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Change in coreboot[master]: cpu/amd/quadcore: Correct checkpatch errors
by Logan Carlson (Code Review) 31 May '17

31 May '17

Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19990 ) Change subject: cpu/amd/quadcore: Correct checkpatch errors ...................................................................... cpu/amd/quadcore: Correct checkpatch errors Correct issues with whitespace found in cpu/amd/quadcore. Change-Id: Idc48d1177db474649cddd8a2f496e330eaabb113 Signed-off-by: Logan Carlson <logancarlson(a)google.com> --- M src/cpu/amd/quadcore/amd_sibling.c M src/cpu/amd/quadcore/quadcore.c M src/cpu/amd/quadcore/quadcore_id.c 3 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19990/1 diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index c4eb50c..526dc0d 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -41,7 +41,7 @@ u32 siblings=0; //get max siblings from all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid = 0; nodeid < nodes; nodeid++) { int j; dev = get_node_pci(nodeid, 3); j = (pci_read_config32(dev, 0xe8) >> 12) & 3; @@ -60,7 +60,7 @@ u32 nodeid; //enable APIC_EXIT_ID all the nodes - for (nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid = 0; nodeid < nodes; nodeid++) { u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); @@ -82,9 +82,11 @@ siblings = get_max_siblings(sysconf.nodes); - if (sysconf.bsp_apicid > 0) { // IOAPIC could start from 0 + if (sysconf.bsp_apicid > 0) { + // IOAPIC could start from 0 return 0; - } else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0 + } else if (sysconf.enabled_apic_ext_id) { + // enabled ext id but bsp = 0 return 1; } @@ -93,7 +95,7 @@ //Construct apicid_base - if ((!disable_siblings) && (siblings>0) ) { + if ((!disable_siblings) && (siblings > 0)) { /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make IOAPIC work. I don't @@ -108,7 +110,7 @@ apicid_base = sysconf.nodes; } - if ((apicid_base+ioapic_num-1)>0xf) { + if ((apicid_base+ioapic_num-1) > 0xf) { // We need to enable APIC EXT ID printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n"); enable_apic_ext_id(sysconf.nodes); diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c index 2f0822e..d4f0dd7 100644 --- a/src/cpu/amd/quadcore/quadcore.c +++ b/src/cpu/amd/quadcore/quadcore.c @@ -34,9 +34,9 @@ dword >>= 12; /* Bit 15 is CmpCap[2] since Revision D. */ if ((cpuid_ecx(0x80000008) & 0xff) > 3) - dword = ((dword & 8) >> 1) | (dword & 3); + dword = ((dword & 8) >> 1) | (dword & 3); else - dword &= 3; + dword &= 3; } return dword; } diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index cd83906..f2a9e1a 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -26,7 +26,7 @@ { msr_t msr; msr = rdmsr(NB_CFG_MSR); - return ( ( msr.hi >> (54-32)) & 1); + return ((msr.hi >> (54-32)) & 1); } u32 get_initial_apicid(void) @@ -75,7 +75,7 @@ * The apicid format varies based on processor revision */ apicid = (cpuid_ebx(1) >> 24) & 0xff; - if ( nb_cfg_54) { + if (nb_cfg_54) { if (fam15h && dual_node) { id.coreid = apicid & 0x1f; id.nodeid = (apicid & 0x60) >> 5; -- To view, visit https://review.coreboot.org/19990 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Idc48d1177db474649cddd8a2f496e330eaabb113 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com>

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coreboot-gerrit May 2017