coreboot-gerrit May 2017

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Change in coreboot[master]: soc/amd: Fix most checkpatch errors
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19986 to look at the new patch set (#2). Change subject: soc/amd: Fix most checkpatch errors ...................................................................... soc/amd: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Changes to agesawrapper.c cause the build to change, so this file is also left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/agesawrapper.h M src/soc/amd/common/agesawrapper_call.h M src/soc/amd/common/amd_pci_util.c M src/soc/amd/common/amd_pci_util.h M src/soc/amd/common/cache_as_ram.inc M src/soc/amd/common/def_callouts.c M src/soc/amd/common/dimmSpd.h M src/soc/amd/common/heapmanager.c M src/soc/amd/common/spi.c M src/soc/amd/stoneyridge/acpi/fch.asl M src/soc/amd/stoneyridge/acpi/lpc.asl M src/soc/amd/stoneyridge/acpi/northbridge.asl M src/soc/amd/stoneyridge/acpi/pci_int.asl M src/soc/amd/stoneyridge/acpi/pcie.asl M src/soc/amd/stoneyridge/acpi/usb.asl M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/dimmSpd.c M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/fadt.c M src/soc/amd/stoneyridge/fixme.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/hudson.c M src/soc/amd/stoneyridge/imc.c M src/soc/amd/stoneyridge/include/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/amd_pci_int_types.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/hudson.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/model_15_init.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sd.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/amd/stoneyridge/uart.c 43 files changed, 801 insertions(+), 670 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19986/2 -- To view, visit https://review.coreboot.org/19986 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee: Pass GPIO setting in amdinitenv
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19839 to look at the new patch set (#4). Change subject: google/kahlee: Pass GPIO setting in amdinitenv ...................................................................... google/kahlee: Pass GPIO setting in amdinitenv GPIOs for I2C3 were being unset in amdinitmid if the GPIO enable table wasn't passed. It had been initialy set in amdinitreset. Pull the GPIO settings into their own file that can be used in bootblock and later stages. Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/Makefile.inc M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c A src/mainboard/google/kahlee/gpio.c 4 files changed, 101 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/19839/4 -- To view, visit https://review.coreboot.org/19839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee: Add ChromeOS SMBIOS Board ID
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19837 to look at the new patch set (#4). Change subject: google/kahlee: Add ChromeOS SMBIOS Board ID ...................................................................... google/kahlee: Add ChromeOS SMBIOS Board ID Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Makefile.inc A src/mainboard/google/kahlee/boardid.c 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/19837/4 -- To view, visit https://review.coreboot.org/19837 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee: Update GPIO table
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19834 to look at the new patch set (#3). Change subject: google/kahlee: Update GPIO table ...................................................................... google/kahlee: Update GPIO table Update GPIO settings based on the schematic. Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c 1 file changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/19834/3 -- To view, visit https://review.coreboot.org/19834 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19755 to look at the new patch set (#4). Change subject: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK ...................................................................... WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK Add dedicated CAR setup and teardown functions and, Kconfig options to force their inclusion into the build. The .S files are effectively duplicated code from the cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. todo: * preserve BIST Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/x86/lapic/Makefile.inc M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/Makefile.inc M src/mainboard/amd/gardenia/OemCustomize.c A src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c A src/mainboard/amd/gardenia/bootblock/OemCustomize.c M src/mainboard/amd/gardenia/romstage.c M src/soc/amd/common/Makefile.inc A src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/Makefile.inc A src/soc/amd/common/block/cpu/car/cache_as_ram.S A src/soc/amd/common/block/cpu/car/exit_car.S M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c A src/soc/amd/stoneyridge/bootblock/fch.c M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/include/soc/hudson.h M src/soc/amd/stoneyridge/include/soc/northbridge.h A src/soc/amd/stoneyridge/romstage.c M src/vendorcode/amd/pi/Makefile.inc 21 files changed, 954 insertions(+), 327 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19755/4 -- To view, visit https://review.coreboot.org/19755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Enable verstage support
by Marshall Dawson (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19756 to look at the new patch set (#4). Change subject: soc/amd/stoneyridge: Enable verstage support ...................................................................... soc/amd/stoneyridge: Enable verstage support Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19756/4 -- To view, visit https://review.coreboot.org/19756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/eve: Update thermal tuning parameters
by Duncan Laurie (Code Review) 31 May '17

31 May '17

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19947 ) Change subject: mb/google/eve: Update thermal tuning parameters ...................................................................... mb/google/eve: Update thermal tuning parameters Modify the DPTF configuration on Eve to relax the severe throttling that is currently applied and allow performance testing to see better results. BUG=b:35581264 TEST=performance tests show better results and thermal tests still pass. Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/19947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/eve/acpi/dptf.asl M src/mainboard/google/eve/devicetree.cb 2 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index eaacb46..8937ee9 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -29,12 +29,12 @@ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_NAME "eMMC" -#define DPTF_TSR3_PASSIVE 55 +#define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_CRITICAL 75 #undef DPTF_ENABLE_FAN_CONTROL @@ -56,19 +56,19 @@ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on Charger */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 }, /* CPU Effect on DRAM */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on eMMC */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 }, /* Charger Throttle Effect on Charger (TSR1) */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, /* Charger Throttle Effect on eMMC (TSR3) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -77,15 +77,15 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 2500, /* PowerLimitMinimum */ - 4500, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 250 /* StepSize */ + 7000, /* PowerLimitMaximum */ + 5000, /* TimeWindowMinimum */ + 5000, /* TimeWindowMaximum */ + 200 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 7000, /* PowerLimitMinimum */ - 7000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e255a7a..81f235f 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -215,7 +215,7 @@ register "speed_shift_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl2_override" = "7" + register "tdp_pl2_override" = "15" register "tcc_offset" = "10" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/19947 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/eve: Add power controls to touchscreen device
by Duncan Laurie (Code Review) 31 May '17

31 May '17

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19946 ) Change subject: mb/google/eve: Add power controls to touchscreen device ...................................................................... mb/google/eve: Add power controls to touchscreen device Instead of having the SMI handler power off the touchscreen on the way into suspend add power resource controls to the ACPI device so the power is managed by the kernel instead of the BIOS. BUG=b:35581264 TEST=manual testing on Eve to ensure that the touchscreen is still functional at boot and after suspend/resume, and that it does not draw power in suspend. Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/19946 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/eve/gpio.h M src/mainboard/google/eve/smihandler.c 3 files changed, 5 insertions(+), 3 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 487dda3..e255a7a 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -233,6 +233,10 @@ register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST_PLUS" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "generic.enable_delay_ms" = "250" register "hid_desc_reg_offset" = "0x1" device i2c 0a on end end diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index b5c2694..f174d9c 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -38,7 +38,6 @@ #define EC_SCI_GPI GPE0_ESPI /* Power rail control signals */ -#define EN_PP3300_DX_TOUCH GPP_C22 #define EN_PP3300_DX_CAM GPP_D12 #ifndef __ACPI__ @@ -117,7 +116,7 @@ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ diff --git a/src/mainboard/google/eve/smihandler.c b/src/mainboard/google/eve/smihandler.c index 879131c..493a334 100644 --- a/src/mainboard/google/eve/smihandler.c +++ b/src/mainboard/google/eve/smihandler.c @@ -29,7 +29,6 @@ static void mainboard_gpio_smi_sleep(u8 slp_typ) { /* Power down the rails on any sleep type */ - gpio_set(EN_PP3300_DX_TOUCH, 0); gpio_set(EN_PP3300_DX_CAM, 0); } -- To view, visit https://review.coreboot.org/19946 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/arm/include/armv7/arch: Correct keyword organization in...
by Philippe Mathieu-Daudé (Code Review) 31 May '17

31 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19991 ) Change subject: arch/arm/include/armv7/arch: Correct keyword organization in cpu.h ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch/arm: Correct checkpatch errors
by Philippe Mathieu-Daudé (Code Review) 31 May '17

31 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19989 ) Change subject: arch/arm: Correct checkpatch errors ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74b68f485adff1e6f0fa433e51e12b59ccea654b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017