coreboot-gerrit May 2017

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Change in coreboot[master]: soc/amd/common: Add tseg size to Kconfig
by build bot (Jenkins) (Code Review) 17 May '17

17 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19750 ) Change subject: soc/amd/common: Add tseg size to Kconfig ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9619/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53873/ : SUCCESS -- To view, visit https://review.coreboot.org/19750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Enable early cbmem
by build bot (Jenkins) (Code Review) 17 May '17

17 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19751 ) Change subject: soc/amd/stoneyridge: Enable early cbmem ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9621/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53874/ : SUCCESS -- To view, visit https://review.coreboot.org/19751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19755 ) Change subject: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK ...................................................................... WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK Add dedicated CAR setup and teardown functions and, Kconfig options to force their inclusion into the build. The .S files are effectively duplicated code from the cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. todo: * clean up BioCallouts.c file * preserve BIST * look for ways to refactor to further clean up files used in bootblock? Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/x86/lapic/Makefile.inc M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/Makefile.inc M src/mainboard/amd/gardenia/romstage.c M src/soc/amd/common/Makefile.inc A src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/Makefile.inc A src/soc/amd/common/block/cpu/car/cache_as_ram.S A src/soc/amd/common/block/cpu/car/exit_car.S M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h A src/soc/amd/stoneyridge/romstage.c M src/vendorcode/amd/pi/Makefile.inc 15 files changed, 366 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19755/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9df2c5f..1525521 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 7ff4eb8..a494512 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -31,6 +31,7 @@ #include "BiosCallOuts.h" #include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/agesawrapper.h" +#include <rules.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -39,7 +40,11 @@ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, +#if ENV_BOOTBLOCK + {AGESA_READ_SPD, agesa_NoopUnsupported }, +#else {AGESA_READ_SPD, agesa_ReadSpd }, +#endif {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, @@ -92,6 +97,9 @@ FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; +#if ENV_BOOTBLOCK + } +#else } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -124,6 +132,7 @@ break; } } +#endif /* ENV_BOOTBLOCK */ printk(BIOS_DEBUG, "Done\n"); return AGESA_SUCCESS; diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index ba5e377..de24187 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -13,6 +13,9 @@ # GNU General Public License for more details. # +bootblock-y += BiosCallOuts.c +bootblock-y += OemCustomize.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 788d3d7..e25adbd 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -13,70 +13,3 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <soc/hudson.h> -#include <amdblocks/psp.h> - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - amd_initmmio(); - hudson_lpc_port80(); - hudson_lpc_decode(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if IS_ENABLED(CONFIG_STONEYRIDGE_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - post_code(0x38); - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - psp_notify_dram(); - - post_code(0x42); - cbmem_initialize_empty(); - - post_code(0x43); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ -} diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 570dab3..fe87504 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -1,6 +1,18 @@ ifeq ($(CONFIG_SOC_AMD_COMMON),y) +subdirs-y += block/ + +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) + +bootblock-y += agesawrapper.c +bootblock-y += def_callouts.c +bootblock-y += heapmanager.c + +else # ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) + cpu_incs-y += $(src)/soc/amd/common/cache_as_ram.inc + +endif # ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) romstage-y += agesawrapper.c romstage-y += def_callouts.c @@ -13,6 +25,6 @@ ramstage-y += heapmanager.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -subdirs-y += ./* +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += ./block endif diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig new file mode 100644 index 0000000..d301eb3 --- /dev/null +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_CAR + bool + default n + help + This option allows you to select how cache-as-ram (CAR) is set up. diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc new file mode 100644 index 0000000..8e6972e --- /dev/null +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S new file mode 100644 index 0000000..6c42a99 --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.inc + * + * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +/* + * XMM map: + * xmm0: BIST + * xmm1: backup ebx -- cpu_init_detected + */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Get the cpu_init_detected */ + mov $1, %eax + cpuid + shr $24, %ebx + + /* Save the BIST result */ + cvtsi2sd %ebp, %xmm0 + + /* for normal part %ebx already contain cpu_init_detected from fallback call */ + + /* Save the cpu_init_detected */ + cvtsi2sd %ebx, %xmm1 + + post_code(0xa1) + + AMD_ENABLE_STACK + + /* Align the stack. */ + and $0xFFFFFFF0, %esp + +#ifdef __x86_64__ + /* switch to 64 bit long mode */ + mov %esi, %ecx + add $0, %ecx # core number + xor %eax, %eax + lea (0x1000+0x23)(%ecx), %edi + mov %edi, (%ecx) + mov %eax, 4(%ecx) + + lea 0x1000(%ecx), %edi + movl $0x000000e3, 0x00(%edi) + movl %eax, 0x04(%edi) + movl $0x400000e3, 0x08(%edi) + movl %eax, 0x0c(%edi) + movl $0x800000e3, 0x10(%edi) + movl %eax, 0x14(%edi) + movl $0xc00000e3, 0x18(%edi) + movl %eax, 0x1c(%edi) + + # load ROM based identity mapped page tables + mov %ecx, %eax + mov %eax, %cr3 + + # enable PAE + mov %cr4, %eax + bts $5, %eax + mov %eax, %cr4 + + # enable long mode + mov $0xC0000080, %ecx + rdmsr + bts $8, %eax + wrmsr + + # enable paging + mov %cr0, %eax + bts $31, %eax + mov %eax, %cr0 + + # use call far to switch to 64-bit code segment + ljmp $0x18, $1f +1: + /* Pass the cpu_init_detected */ + cvtsd2si %xmm1, %esi + + /* Pass the BIST result */ + cvtsd2si %xmm0, %edi + +#else + + /* Restore the BIST result */ + cvtsd2si %xmm0, %edx + + /* Restore the cpu_init_detected */ + cvtsd2si %xmm1, %ebx +#endif + + /* Must maintain 16-byte stack alignment here. */ + pushl $0x0 + pushl $0x0 + pushl %ebx /* init detected */ + pushl %edx /* bist */ + +before_carstage: + post_code(0xa2) + + call bootblock_c_entry + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S new file mode 100644 index 0000000..46802d9 --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gcccar.inc> +#include <cpu/x86/cache.h> + +.code32 +.globl chipset_teardown_car + +chipset_teardown_car: + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3<<9), %eax + movl %eax, %cr4 + + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + + ret diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 74e0c92..acc4bc0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -42,6 +42,9 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_PSP + select SOC_AMD_COMMON_BLOCK_CAR + select C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CONSOLE config UDELAY_LAPIC_FIXED_FSB int @@ -59,6 +62,20 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + depends on C_ENVIRONMENT_BOOTBLOCK + hex + default 0x4000 + help + This symbol gets picked up in car.ld when CONFIG_C_ENVIRONMENT_BOOTBLOCK + is used. AMD doesn't seem to use this currently. + + todo: Can this and the other 2 DCACHE_RAM_ symbols eventually be + condensed? + + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config CPU_ADDR_BITS int default 48 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index bc172f1..031c19b 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -37,6 +37,12 @@ subdirs-y += ../../../cpu/x86/pae subdirs-y += ../../../cpu/x86/smm +bootblock-y += early_setup.c +bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c +bootblock-y += fixme.c +bootblock-y += bootblock.c + +romstage-y += romstage.c romstage-y += early_setup.c romstage-y += dimmSpd.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c new file mode 100644 index 0000000..93c181c --- /dev/null +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2017 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include <cpu/amd/car.h> +#include <bootblock_common.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <timestamp.h> +#include <soc/hudson.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + amd_initmmio(); + hudson_lpc_port80(); + hudson_lpc_decode(); + + post_code(0x90); + if (CONFIG_STONEYRIDGE_UART) + configure_hudson_uart(); +} + +void bootblock_soc_init(void) +{ + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + // todo: where to get BIST + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + + post_code(0x38); + AGESAWRAPPER(amdinitearly); +} diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 9ecbb13..a9aa1b1 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -23,4 +23,7 @@ void fam15_finalize(void *chip_info); void setup_uma_memory(void); +/* todo: remove this when postcar stage is in place */ +asmlinkage void chipset_teardown_car(void); + #endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c new file mode 100644 index 0000000..b783bd6 --- /dev/null +++ b/src/soc/amd/stoneyridge/romstage.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <soc/northbridge.h> +#include <soc/hudson.h> +#include <amdblocks/psp.h> + +asmlinkage void car_stage_entry(void) +{ + console_init(); + + if (boot_cpu()) + amd_initmmio(); + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + psp_notify_dram(); + + post_code(0x42); + cbmem_initialize_empty(); + + /* This writes contents to DRAM backing before teardown. + * todo: move to postcar implementation + */ + chipset_teardown_car(); + + post_code(0x43); + AGESAWRAPPER(amdinitenv); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +} diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 5c0f08d..1f77ccd 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -145,6 +145,7 @@ @printf " AGESA $(subst $(obj)/,,$(@))\n" ar rcs $@ $+ +bootblock-libs += $(obj)/agesa/libagesa.a romstage-libs += $(obj)/agesa/libagesa.a ramstage-libs += $(obj)/agesa/libagesa.a -- To view, visit https://review.coreboot.org/19755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Enable verstage support
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19756 ) Change subject: soc/amd/stoneyridge: Enable verstage support ...................................................................... soc/amd/stoneyridge: Enable verstage support Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/cpu/x86/lapic/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19756/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 1525521..2cd867d 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +verstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index acc4bc0..650ee03 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -38,6 +38,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE select UDELAY_LAPIC + select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK @@ -46,6 +47,12 @@ select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE +config VBOOT + select AMDFW_OUTSIDE_CBFS + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + config UDELAY_LAPIC_FIXED_FSB int default 200 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 031c19b..ff21f59 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -53,6 +53,9 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += memmap.c +verstage-y += reset.c +verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c + ramstage-y += chip.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -- To view, visit https://review.coreboot.org/19756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/gardenia: Add PSP DRAM notify to romstage
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19754 ) Change subject: amd/gardenia: Add PSP DRAM notify to romstage ...................................................................... amd/gardenia: Add PSP DRAM notify to romstage Change-Id: I6ccbbee00aab947079c3471fcf83ae9a66c01d59 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/romstage.c R src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/psp/psp.c 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19754/1 diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index d58109e..788d3d7 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -24,6 +24,7 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <soc/hudson.h> +#include <amdblocks/psp.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -64,9 +65,12 @@ AGESAWRAPPER(amdinitpost); post_code(0x41); - cbmem_initialize_empty(); + psp_notify_dram(); post_code(0x42); + cbmem_initialize_empty(); + + post_code(0x43); AGESAWRAPPER(amdinitenv); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); diff --git a/src/soc/amd/common/block/psp/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h similarity index 100% rename from src/soc/amd/common/block/psp/psp.h rename to src/soc/amd/common/block/include/amdblocks/psp.h diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index c75b92f..b22161d 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -18,7 +18,7 @@ #include <cbmem.h> #include <device/pci_def.h> #include <console/console.h> -#include "psp.h" +#include <amdblocks/psp.h> static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; static const char *psp_status_halted = "error: PSP in halted state"; -- To view, visit https://review.coreboot.org/19754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6ccbbee00aab947079c3471fcf83ae9a66c01d59 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add initial support for AMD PSP
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19753 ) Change subject: soc/amd/common: Add initial support for AMD PSP ...................................................................... soc/amd/common: Add initial support for AMD PSP Add files for supporting the BIOS->PSP communication not covered by AGESA. The first command implemented notifies the PSP that DRAM is ready. This patch also introduces the amd/common/block directory structure similar to intel/common/block. Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/Kconfig M src/soc/amd/common/Makefile.inc A src/soc/amd/common/block/Kconfig A src/soc/amd/common/block/Makefile.inc A src/soc/amd/common/block/psp/Kconfig A src/soc/amd/common/block/psp/Makefile.inc A src/soc/amd/common/block/psp/psp.c A src/soc/amd/common/block/psp/psp.h M src/soc/amd/stoneyridge/Kconfig 9 files changed, 327 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19753/1 diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig index d4fe1f7..debedac 100644 --- a/src/soc/amd/common/Kconfig +++ b/src/soc/amd/common/Kconfig @@ -9,4 +9,6 @@ bool default n +source "src/soc/amd/common/block/Kconfig" + endif # SOC_AMD_COMMON diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 9d4588d..570dab3 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -13,4 +13,6 @@ ramstage-y += heapmanager.c ramstage-$(CONFIG_SPI_FLASH) += spi.c +subdirs-y += ./* + endif diff --git a/src/soc/amd/common/block/Kconfig b/src/soc/amd/common/block/Kconfig new file mode 100644 index 0000000..86150ed --- /dev/null +++ b/src/soc/amd/common/block/Kconfig @@ -0,0 +1,11 @@ +config SOC_AMD_COMMON_BLOCK + bool + help + SoC driver for AMD common IP code + +if SOC_AMD_COMMON_BLOCK + +comment "AMD SoC Common IP Code" +source "src/soc/amd/common/block/*/Kconfig" + +endif diff --git a/src/soc/amd/common/block/Makefile.inc b/src/soc/amd/common/block/Makefile.inc new file mode 100644 index 0000000..33c8822 --- /dev/null +++ b/src/soc/amd/common/block/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK),y) + +subdirs-y += ./* + +CPPFLAGS_common += -I$(src)/soc/amd/common/block/include/ + +endif diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig new file mode 100644 index 0000000..69958f2 --- /dev/null +++ b/src/soc/amd/common/block/psp/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_PSP + bool + default n + help + This option builds in the Platform Security Processor initialization + functions. diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc new file mode 100644 index 0000000..eebba16 --- /dev/null +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c new file mode 100644 index 0000000..c75b92f --- /dev/null +++ b/src/soc/amd/common/block/psp/psp.c @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <delay.h> +#include <cbmem.h> +#include <device/pci_def.h> +#include <console/console.h> +#include "psp.h" + +static const char *psp_status_nobase = "error: PSP BAR3 not assigned"; +static const char *psp_status_halted = "error: PSP in halted state"; +static const char *psp_status_recovery = "error: PSP recovery required"; +static const char *psp_status_errcmd = "error sending command"; +static const char *psp_status_init_timeout = "error: PSP init timeout"; +static const char *psp_status_cmd_timeout = "error: PSP command timeout"; +static const char *psp_status_noerror = ""; + +static const char *status_to_string(int err) +{ + switch (err) { + case -PSPSTS_NOBASE: + return psp_status_nobase; + case -PSPSTS_HALTED: + return psp_status_halted; + case -PSPSTS_RECOVERY: + return psp_status_recovery; + case -PSPSTS_SEND_ERROR: + return psp_status_errcmd; + case -PSPSTS_INIT_TIMEOUT: + return psp_status_init_timeout; + case -PSPSTS_CMD_TIMEOUT: + return psp_status_cmd_timeout; + default: + return psp_status_noerror; + } +} + +static struct psp_mbox *get_mbox_address(void) +{ + UINT32 base; /* UINT32 for compatibility with PspBaseLib */ + BOOLEAN bar3_status; + uintptr_t baseptr; + + bar3_status = GetPspBar3Addr(&base); + if (!bar3_status) { + PspBarInitEarly(); + bar3_status = GetPspBar3Addr(&base); + } + if (!bar3_status) + return NULL; + + baseptr = base; + return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); +} + +static u32 rd_mbox_sts(struct psp_mbox *mbox) +{ + return read32(&mbox->mbox_status); +} + +static void wr_mbox_cmd(struct psp_mbox *mbox, u32 cmd) +{ + write32(&mbox->mbox_command, cmd); +} + +static u32 rd_mbox_cmd(struct psp_mbox *mbox) +{ + return read32(&mbox->mbox_command); +} + +static void wr_mbox_cmd_resp(struct psp_mbox *mbox, void *buffer) +{ + write64(&mbox->cmd_response, (uintptr_t)buffer); +} + +static u32 rd_resp_sts(struct mbox_default_buffer *buffer) +{ + return read32(&buffer->header.status); +} + +static int wait_initialized(struct psp_mbox *mbox) +{ + long int usec_wait = 10000000; /* arbitrary 10 seconds */ + + do { + if (rd_mbox_sts(mbox) & STATUS_INITIALIZED) + return 0; + udelay(1); + } while (usec_wait--); + + return -PSPSTS_INIT_TIMEOUT; +} + +static int wait_command(struct psp_mbox *mbox) +{ + long int usec_wait = 1000000; /* arbitrary 1 second */ + + do { + if (!rd_mbox_cmd(mbox)) + return 0; + udelay(1); + } while (usec_wait--); + + return -PSPSTS_CMD_TIMEOUT; +} + +static int send_psp_command(u32 command, void *buffer) +{ + u32 command_reg; + int status = 0; + + struct psp_mbox *mbox = get_mbox_address(); + if (!mbox) + return -PSPSTS_NOBASE; + + command_reg = pci_read_config32(PSP_DEV, PCI_COMMAND); + pci_write_config32(PSP_DEV, PCI_COMMAND, command_reg | + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* check for PSP error conditions */ + if (rd_mbox_sts(mbox) & STATUS_HALT) { + status = -PSPSTS_HALTED; + goto exit; + } + if (rd_mbox_sts(mbox) & STATUS_RECOVERY) { + status = -PSPSTS_RECOVERY; + goto exit; + } + + /* PSP must be finished with init and ready to accept a command */ + if (wait_initialized(mbox)) { + status = -PSPSTS_INIT_TIMEOUT; + goto exit; + } + if (wait_command(mbox)) { + status = -PSPSTS_CMD_TIMEOUT; + goto exit; + } + + /* set address of command-response buffer and write command register */ + wr_mbox_cmd_resp(mbox, buffer); + wr_mbox_cmd(mbox, command); + + /* PSP clears command register when complete */ + if (wait_command(mbox)) { + status = -PSPSTS_CMD_TIMEOUT; + goto exit; + } + + /* check delivery status */ + if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED)) { + status = -PSPSTS_SEND_ERROR; + goto exit; + } +exit: + /* restore command register to original value */ + pci_write_config32(PSP_DEV, PCI_COMMAND, command_reg); + return status; +} + +/* + * Notify the PSP that DRAM is present. Upon receiving this command, the PSP + * will load its OS into fenced DRAM that is not accessible to the x86 cores. + */ +int psp_notify_dram(void) +{ + struct mbox_default_buffer buffer; + int cmd_status; + + printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); + + buffer.header.size = sizeof(struct mbox_default_buffer); + buffer.header.status = 0; /* PSP does not report status for this cmd */ + + cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); + + /* buffer's status shouldn't change but report it if it does */ + if (rd_resp_sts(&buffer)) + printk(BIOS_DEBUG, "buffer status=0x%x ", + rd_resp_sts(&buffer)); + if (cmd_status) + printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + else + printk(BIOS_DEBUG, "OK\n"); + + return cmd_status; +} diff --git a/src/soc/amd/common/block/psp/psp.h b/src/soc/amd/common/block/psp/psp.h new file mode 100644 index 0000000..9ce62f9 --- /dev/null +++ b/src/soc/amd/common/block/psp/psp.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMD_PSP_H +#define AMD_PSP_H + +#include <stdint.h> +#include <Porting.h> +#include <Proc/Psp/PspBaseLib/PspBaseLib.h> + +/* x86 to PSP commands */ +#define MBOX_BIOS_CMD_DRAM_INFO 0x01 +#define MBOX_BIOS_CMD_SMM_INFO 0x02 +#define MBOX_BIOS_CMD_SX_INFO 0x03 +#define MBOX_BIOS_CMD_RSM_INFO 0x04 +#define MBOX_BIOS_CMD_PSP_QUERY 0x05 +#define MBOX_BIOS_CMD_BOOT_DONE 0x06 +#define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 +#define MBOX_BIOS_CMD_C3_DATA_INFO 0x08 +#define MBOX_BIOS_CMD_NOP 0x09 +#define MBOX_BIOS_CMD_ABORT 0xfe + +/* generic PSP interface status */ +#define STATUS_INITIALIZED 0x1 +#define STATUS_ERROR 0x2 +#define STATUS_TERMINATED 0x4 +#define STATUS_HALT 0x8 +#define STATUS_RECOVERY 0x10 + +/* psp_mbox consists of hardware registers beginning at PSPx000070 + * mbox_command: BIOS->PSP command, cleared by PSP when complete + * mbox_status: BIOS->PSP interface status + * cmd_response: pointer to command/response buffer + */ +struct psp_mbox { + u32 mbox_command; + u32 mbox_status; + u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ +} __attribute__ ((packed)); + +/* command/response format, BIOS builds this in memory + * mbox_buffer_header: generic header + * mbox_buffer: command-specific buffer format + * + * AMD reference code aligns and pads all buffers to 32 bytes. + */ +struct mbox_buffer_header { + u32 size; /* total size of buffer */ + u32 status; /* command status, filled by PSP if applicable */ +} __attribute__ ((packed)); + +/* command-specific buffer definitions: see NDA document #54267 + * todo: create new definitions here for additional c2p_mbox_command commands + */ + +struct mbox_default_buffer { /* command-response buffer unused by command */ + struct mbox_buffer_header header; +} __attribute__ ((packed,aligned(32))); + +/* send_psp_command() error codes */ +#define PSPSTS_SUCCESS 0 +#define PSPSTS_NOBASE 1 +#define PSPSTS_HALTED 2 +#define PSPSTS_RECOVERY 3 +#define PSPSTS_SEND_ERROR 4 +#define PSPSTS_INIT_TIMEOUT 5 +#define PSPSTS_CMD_TIMEOUT 6 + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#include <device/pci_def.h> +#define PSP_DEV dev_find_slot(0, PCI_DEVFN(PSP_PCI_DEV, PSP_PCI_FN)) +#else +#include <arch/io.h> +#define PSP_DEV PCI_DEV(0, PSP_PCI_DEV, PSP_PCI_FN) +#endif + +/* BIOS-to-PSP functions return 0 if successful, else negative value */ +int psp_notify_dram(void); + +#endif /* AMD_PSP_H */ diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6584fbb..74e0c92 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -37,9 +37,11 @@ select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE - select SOC_AMD_COMMON - select SOC_AMD_PI select UDELAY_LAPIC + select SOC_AMD_PI + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_PSP config UDELAY_LAPIC_FIXED_FSB int -- To view, visit https://review.coreboot.org/19753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/gardenia: Init cbmem in romstage
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19752 ) Change subject: amd/gardenia: Init cbmem in romstage ...................................................................... amd/gardenia: Init cbmem in romstage Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/romstage.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/19752/1 diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 1e4e538..d58109e 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -17,6 +17,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> +#include <cbmem.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> @@ -61,7 +62,11 @@ post_code(0x40); AGESAWRAPPER(amdinitpost); + post_code(0x41); + cbmem_initialize_empty(); + + post_code(0x42); AGESAWRAPPER(amdinitenv); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); -- To view, visit https://review.coreboot.org/19752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Enable early cbmem
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19751 ) Change subject: soc/amd/stoneyridge: Enable early cbmem ...................................................................... soc/amd/stoneyridge: Enable early cbmem Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/memmap.c A src/soc/amd/stoneyridge/memmap.h M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 111 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/19751/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 9c184ed..6584fbb 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -35,7 +35,6 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET select LAPIC_MONOTONIC_TIMER - select LATE_CBMEM_INIT select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE select SOC_AMD_COMMON diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 3a6ae84..bc172f1 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += smbus.c romstage-y += smbus_spd.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c +romstage-y += memmap.c ramstage-y += chip.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c @@ -68,6 +69,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c ramstage-y += usb.c +ramstage-y += memmap.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c new file mode 100644 index 0000000..8272a40 --- /dev/null +++ b/src/soc/amd/stoneyridge/memmap.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <commonlib/helpers.h> +#include <cbmem.h> +#include "memmap.h" + +static int installed_gb(void) +{ + uint32_t sysmem_mb; + msr_t topmem = rdmsr(TOP_MEM); + msr_t topmem2 = rdmsr(TOP_MEM2); + + /* Ignore 16MB allocated for C6 when finding UMA size */ + sysmem_mb = (topmem.lo + (16ull * MiB)) / MiB; + + if (topmem2.hi) + sysmem_mb += ((topmem2.hi - 1) * (GiB / MiB * 4) + + (topmem2.lo / MiB)); + + return sysmem_mb / (GiB / MiB); +} + +/* + * Return the size likely assigned to UMA when UMA_AUTO is specified. + * This is the only setting the wrapper currently implements. Refer to the + * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the + * following recommended configurations: + * Total system memory UMASize + * 6G+ 1024M + * 4G 512M + * 2G 256M + */ +size_t uma_size_auto(void) +{ + int sysmem_gb = installed_gb(); + + if (!IS_ENABLED(CONFIG_GFXUMA)) + return 0; + else if (sysmem_gb >= 6) + return 1024 * MiB; + else if (sysmem_gb >= 4) + return 512 * MiB; + else + return 256 * MiB; +} + +/* + * The BinaryPI image is compiled to always assign UMA below 4GB. It will + * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller. + */ +uintptr_t uma_base_auto(void) +{ + msr_t topmem = rdmsr(TOP_MEM); + return topmem.lo - uma_size_auto(); +} + +/* + * todo: make more flexible if agesawrapper.c changes. The wrapper + * currently uses CONFIG_GFXUMA to set UMA_AUTO or UMA_NONE and provides + * no opportunity for the mainboard to override it. + */ +void *cbmem_top(void) +{ + msr_t tom = rdmsr(TOP_MEM); + + if (!tom.lo) + return 0; + else + return (void *)(uma_base_auto() - CONFIG_SMM_TSEG_SIZE); +} diff --git a/src/soc/amd/stoneyridge/memmap.h b/src/soc/amd/stoneyridge/memmap.h new file mode 100644 index 0000000..a57dc31 --- /dev/null +++ b/src/soc/amd/stoneyridge/memmap.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_AMD_MEMMAP_H +#define NORTHBRIDGE_AMD_MEMMAP_H + +uintptr_t uma_base_auto(void); +size_t uma_size_auto(void); + +#endif /* NORTHBRIDGE_AMD_MEMMAP_H */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 1bc7a35..9c75f0d 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -623,12 +623,8 @@ ramtop = mmio_basek * 1024; } - if (IS_ENABLED(CONFIG_GFXUMA)) { - set_top_of_ram(uma_memory_base); + if (IS_ENABLED(CONFIG_GFXUMA)) uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); - } else { - set_top_of_ram(ramtop); - } for (link = dev->link_list; link; link = link->next) { if (link->children) { -- To view, visit https://review.coreboot.org/19751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add tseg size to Kconfig
by Marshall Dawson (Code Review) 17 May '17

17 May '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19750 ) Change subject: soc/amd/common: Add tseg size to Kconfig ...................................................................... soc/amd/common: Add tseg size to Kconfig Add a SMM_TSEG_SIZE symbol that can be used in top of memory calculations. Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/19750/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d07833d..9c184ed 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -263,4 +263,9 @@ to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. +config SMM_TSEG_SIZE + hex + default 0x800000 if HAVE_SMI_HANDLER + default 0x0 + endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 -- To view, visit https://review.coreboot.org/19750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mainboard/intel/glkrvp: use correct emmc tuning parameters
by Bora Guvendik (Code Review) 17 May '17

17 May '17

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/19721 ) Change subject: mainboard/intel/glkrvp: use correct emmc tuning parameters ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19721/1//COMMIT_MSG Commit Message: PS1, Line 9: change the emmc tuning parameters for rvp board > Where do you get the “correct” values from? Using FSP defaults for glkrvp instead of the parameters for reef -- To view, visit https://review.coreboot.org/19721 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I92e29a313d39de8bd549692a0a1b7817010df5f9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017