coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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3888 discussions

Change in coreboot[master]: arch/x86: Add function to determine if we're currently runni...
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19787 ) Change subject: arch/x86: Add function to determine if we're currently running from CAR ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9728/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53991/ : SUCCESS -- To view, visit https://review.coreboot.org/19787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arch: Unify basic cache clearing API
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19788 ) Change subject: arch: Unify basic cache clearing API ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9729/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53992/ : SUCCESS -- To view, visit https://review.coreboot.org/19788 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: tegra210: Remove fake cpu_reset()
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19786 ) Change subject: tegra210: Remove fake cpu_reset() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9726/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53989/ : SUCCESS -- To view, visit https://review.coreboot.org/19786 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: arm64: Align cache maintenance code with libpayload and ARM32
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19785 ) Change subject: arm64: Align cache maintenance code with libpayload and ARM32 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9727/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53990/ : SUCCESS -- To view, visit https://review.coreboot.org/19785 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE fur...
by build bot (Jenkins) (Code Review) 18 May '17

18 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19784 ) Change subject: rk3399: Reshuffle memlayout to move PRERAM_CBMEM_CONSOLE further back ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9725/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53988/ : SUCCESS -- To view, visit https://review.coreboot.org/19784 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifc1e568cda334394134bba9eba75088032d2ff13 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: Consolidate reset API, add generic reset_prepare mechanism
by Julius Werner (Code Review) 18 May '17

18 May '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19789 to review the following change. Change subject: Consolidate reset API, add generic reset_prepare mechanism ...................................................................... Consolidate reset API, add generic reset_prepare mechanism There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/reset.h M src/lib/Makefile.inc A src/lib/reset.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/google/cosmos/reset.c M src/mainboard/google/foster/reset.c M src/mainboard/google/gale/reset.c M src/mainboard/google/gru/reset.c M src/mainboard/google/nyan/reset.c M src/mainboard/google/nyan_big/reset.c M src/mainboard/google/nyan_blaze/reset.c M src/mainboard/google/purin/reset.c M src/mainboard/google/rotor/reset.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/storm/reset.c M src/mainboard/google/veyron/reset.c M src/mainboard/google/veyron_mickey/reset.c M src/mainboard/google/veyron_rialto/reset.c M src/northbridge/via/cx700/reset.c M src/northbridge/via/vx900/northbridge.c M src/soc/dmp/vortex86ex/hard_reset.c M src/soc/imgtec/pistachio/reset.c M src/soc/intel/apollolake/reset.c M src/soc/intel/baytrail/reset.c M src/soc/intel/broadwell/reset.c M src/soc/intel/common/reset.c M src/soc/intel/fsp_baytrail/reset.c M src/soc/intel/fsp_broadwell_de/reset.c M src/soc/intel/sch/reset.c M src/soc/intel/skylake/reset.c M src/soc/mediatek/mt8173/wdt.c M src/soc/samsung/exynos5250/power.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/cimx/sb700/reset.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb900/reset.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/sb600/early_setup.c M src/southbridge/amd/sb600/reset.c M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/amd/sb800/reset.c M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/broadcom/bcm5785/reset.c M src/southbridge/intel/bd82x6x/reset.c M src/southbridge/intel/fsp_bd82x6x/reset.c M src/southbridge/intel/fsp_i89xx/reset.c M src/southbridge/intel/fsp_rangeley/reset.c M src/southbridge/intel/i3100/reset.c M src/southbridge/intel/i82801ax/reset.c M src/southbridge/intel/i82801bx/reset.c M src/southbridge/intel/i82801dx/reset.c M src/southbridge/intel/i82801ex/reset.c M src/southbridge/intel/i82801gx/reset.c M src/southbridge/intel/lynxpoint/reset.c M src/southbridge/nvidia/ck804/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/ck804/reset.c M src/southbridge/nvidia/mcp55/early_ctrl.c M src/southbridge/nvidia/mcp55/reset.c M src/southbridge/sis/sis966/early_ctrl.c M src/southbridge/sis/sis966/reset.c 68 files changed, 197 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/19789/1 diff --git a/src/include/reset.h b/src/include/reset.h index f7501b5..cac853c 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,15 +1,33 @@ #ifndef RESET_H #define RESET_H -#if CONFIG_HAVE_HARD_RESET -void hard_reset(void); -#else -#define hard_reset() do {} while (0) -#endif -void soft_reset(void); -void cpu_reset(void); +/* Generic reset functions. Call from code that wants to trigger a reset. */ + +/* Board-level reset. Resets SoC and other components (e.g. TPM). */ +__attribute__((noreturn)) void hard_reset(void); /* Some Intel SoCs use a special reset that is specific to SoC */ -void global_reset(void); -/* Some Intel SoCs may need to prepare/wait before reset */ -void reset_prepare(void); +__attribute__((noreturn)) void global_reset(void); +/* TODO: come up with clear distinctions for below reset types. */ +__attribute__((noreturn)) void soft_reset(void); +__attribute__((noreturn)) void cpu_reset(void); + +/* Reset implementations. Implement these in SoC or mainboard code. Implement + at least hard_reset() if possible, others fall back to it if necessary. */ +void do_hard_reset(void); +void do_soft_reset(void); +void do_cpu_reset(void); +void do_global_reset(void); + +enum reset_type { /* listed in order of softness */ + HARD_RESET, + GLOBAL_RESET, + SOFT_RESET, + CPU_RESET, +}; + +/* Callback that an SoC may override to perform special actions before reset. + Take into account that softer resets may fall back to harder resets if not + implemented... this will *not* trigger another callback! */ +void soc_reset_prepare(enum reset_type reset_type); + #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 55f5960..d40b615 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -220,6 +220,13 @@ ramstage-y += halt.c smm-y += halt.c +bootblock-y += reset.c +verstage-y += reset.c +romstage-y += reset.c +postcar-y += reset.c +ramstage-y += reset.c +smm-y += reset.c + postcar-y += bootmode.c postcar-y += boot_device.c postcar-y += cbfs.c diff --git a/src/lib/reset.c b/src/lib/reset.c new file mode 100644 index 0000000..aafebb7 --- /dev/null +++ b/src/lib/reset.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <console/console.h> +#include <halt.h> +#include <reset.h> + +__attribute__((noreturn)) static void __hard_reset(void) { + if (IS_ENABLED(CONFIG_HAVE_HARD_RESET)) + do_hard_reset(); + else + printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n"); + halt(); +} + +/* Not all platforms implement all reset types. Fall back to the next-higher + * level of reset by default. */ +__attribute__((weak)) void do_global_reset(void) { __hard_reset(); } +__attribute__((weak)) void do_soft_reset(void) { do_global_reset(); } +__attribute__((weak)) void do_cpu_reset(void) { do_soft_reset(); } + +__attribute__((weak)) void soc_reset_prepare(enum reset_type rt) { /* no-op */ } + +void hard_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + soc_reset_prepare(HARD_RESET); + dcache_clean_all(); + __hard_reset(); +} + +void global_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + soc_reset_prepare(GLOBAL_RESET); + dcache_clean_all(); + do_global_reset(); + halt(); +} + +void soft_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + soc_reset_prepare(SOFT_RESET); + dcache_clean_all(); + do_soft_reset(); + halt(); +} + +void cpu_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + soc_reset_prepare(CPU_RESET); + dcache_clean_all(); + do_cpu_reset(); + halt(); +} diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 3601e50..a19b46a 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -55,7 +55,7 @@ } #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { uint8_t tmp; diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index fdb8577..706b859 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -55,7 +55,7 @@ } #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { uint8_t tmp; diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index f1477c3..1df033a 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -53,7 +53,7 @@ } #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { uint8_t tmp; diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 7864f96..13113b4 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -81,7 +81,7 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" -void soft_reset(void) +void do_soft_reset(void) { uint8_t tmp; diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 89948b7..61d7488 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -64,7 +64,7 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" -void soft_reset(void) +void do_soft_reset(void) { uint8_t tmp; diff --git a/src/mainboard/google/cosmos/reset.c b/src/mainboard/google/cosmos/reset.c index e01c741..16ef5f1 100644 --- a/src/mainboard/google/cosmos/reset.c +++ b/src/mainboard/google/cosmos/reset.c @@ -15,8 +15,6 @@ #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { - while (1) - ; } diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c index df16b78..1b9e9e9 100644 --- a/src/mainboard/google/foster/reset.c +++ b/src/mainboard/google/foster/reset.c @@ -18,8 +18,7 @@ #include <gpio.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO(I5), 0); - while(1); } diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c index d37051a..23d83bf 100644 --- a/src/mainboard/google/gale/reset.c +++ b/src/mainboard/google/gale/reset.c @@ -19,7 +19,7 @@ #include <soc/iomap.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { /* * At boot time the boot loaders would have set a magic cookie diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c index bd06923..0311d58 100644 --- a/src/mainboard/google/gru/reset.c +++ b/src/mainboard/google/gru/reset.c @@ -18,9 +18,7 @@ #include "board.h" -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO_RESET, 1); - while (1) - ; } diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c index 9612d56..ee36292 100644 --- a/src/mainboard/google/nyan/reset.c +++ b/src/mainboard/google/nyan/reset.c @@ -17,8 +17,7 @@ #include <gpio.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO(I5), 0); - while(1); } diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c index 9612d56..ee36292 100644 --- a/src/mainboard/google/nyan_big/reset.c +++ b/src/mainboard/google/nyan_big/reset.c @@ -17,8 +17,7 @@ #include <gpio.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO(I5), 0); - while(1); } diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c index 9612d56..ee36292 100644 --- a/src/mainboard/google/nyan_blaze/reset.c +++ b/src/mainboard/google/nyan_blaze/reset.c @@ -17,8 +17,7 @@ #include <gpio.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO(I5), 0); - while(1); } diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c index 5497175..3667bbf 100644 --- a/src/mainboard/google/purin/reset.c +++ b/src/mainboard/google/purin/reset.c @@ -15,8 +15,6 @@ #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { - while (1) - ; } diff --git a/src/mainboard/google/rotor/reset.c b/src/mainboard/google/rotor/reset.c index 37c2db7..fc97f2d 100644 --- a/src/mainboard/google/rotor/reset.c +++ b/src/mainboard/google/rotor/reset.c @@ -16,7 +16,7 @@ #include <reset.h> #include <soc/reset.h> -void hard_reset(void) +void do_hard_reset(void) { mvmap2315_reset(); } diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c index f875829..fc9a0b6 100644 --- a/src/mainboard/google/smaug/reset.c +++ b/src/mainboard/google/smaug/reset.c @@ -18,9 +18,7 @@ #include "gpio.h" -void hard_reset(void) +void do_hard_reset(void) { gpio_output(AP_SYS_RESET_L, 0); - while (1) - ; } diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c index 94dcd4b..d8f2527 100644 --- a/src/mainboard/google/storm/reset.c +++ b/src/mainboard/google/storm/reset.c @@ -37,12 +37,9 @@ write32(APCS_WDT0_BITE_TIME, RESET_WDT_BITE_TIME); write32(APCS_WDT0_EN, 1); write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1); - - for (;;) - ; } -void hard_reset(void) +void do_hard_reset(void) { wdog_reset(); } diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c index 0d11e76..a937aff 100644 --- a/src/mainboard/google/veyron/reset.c +++ b/src/mainboard/google/veyron/reset.c @@ -19,8 +19,7 @@ #include "board.h" -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO_RESET, 1); - while (1); } diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c index 0d11e76..a937aff 100644 --- a/src/mainboard/google/veyron_mickey/reset.c +++ b/src/mainboard/google/veyron_mickey/reset.c @@ -19,8 +19,7 @@ #include "board.h" -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO_RESET, 1); - while (1); } diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c index cf3a6d8..a937aff 100644 --- a/src/mainboard/google/veyron_rialto/reset.c +++ b/src/mainboard/google/veyron_rialto/reset.c @@ -19,9 +19,7 @@ #include "board.h" -void hard_reset(void) +void do_hard_reset(void) { gpio_output(GPIO_RESET, 1); - while (1) - ; } diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c index b3c2a65..8a62759 100644 --- a/src/northbridge/via/cx700/reset.c +++ b/src/northbridge/via/cx700/reset.c @@ -16,7 +16,7 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { outb((1 << 2) | (1 << 1), 0xcf9); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 7429c4f..5aa1d7d 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -43,7 +43,7 @@ * remapping mechanism will overflow, the effects of which are unknown. */ -void hard_reset(void) +void do_hard_reset(void) { outb((1 << 2) | (1 << 1), 0xcf9); } diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c index 9b9c426..fe127aa 100644 --- a/src/soc/dmp/vortex86ex/hard_reset.c +++ b/src/soc/dmp/vortex86ex/hard_reset.c @@ -16,6 +16,6 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { } diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c index fc581df..c0e9105 100644 --- a/src/soc/imgtec/pistachio/reset.c +++ b/src/soc/imgtec/pistachio/reset.c @@ -20,7 +20,7 @@ #define PISTACHIO_WD_ADDR 0xB8102100 #define PISTACHIO_WD_SW_RST_OFFSET 0x0000 -void hard_reset(void) +void do_hard_reset(void) { /* Generate system reset */ write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 56273cc..15e78fe 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -23,13 +23,13 @@ #define CSE_WAIT_MAX_MS 1000 -void global_reset(void) +void do_global_reset(void) { global_reset_enable(1); - hard_reset(); + do_hard_reset(); } -void reset_prepare(void) +void soc_reset_prepare(enum reset_type reset_type) { struct stopwatch sw; diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c index fd38f61..e38a2e6 100644 --- a/src/soc/intel/baytrail/reset.c +++ b/src/soc/intel/baytrail/reset.c @@ -29,13 +29,13 @@ outb(RST_CPU | SYS_RST, RST_CNT); } -void soft_reset(void) +void do_soft_reset(void) { /* Sends INIT# to CPU */ outb(RST_CPU, RST_CNT); } -void hard_reset(void) +void do_hard_reset(void) { /* Don't power cycle on hard_reset(). It's not really clear what the * semantics should be for the meaning of hard_reset(). */ diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c index e4d01c2..ad90dcd 100644 --- a/src/soc/intel/broadwell/reset.c +++ b/src/soc/intel/broadwell/reset.c @@ -28,12 +28,12 @@ * with ETR[20] set. */ -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index e9be185..ea9b7f1 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -25,39 +25,22 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) -#ifdef __ROMCC__ -#define WEAK -#else -#define WEAK __attribute__((weak)) -#endif - -void WEAK reset_prepare(void) { /* do nothing */ } - #if IS_ENABLED(CONFIG_HAVE_HARD_RESET) -void hard_reset(void) +void do_hard_reset(void) { - reset_prepare(); /* S0->S5->S0 trip. */ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); - while (1) - hlt(); } #endif -void soft_reset(void) +void do_soft_reset(void) { - reset_prepare(); /* PMC_PLTRST# asserted. */ outb(RST_CPU | SYS_RST, RST_CNT); - while (1) - hlt(); } -void cpu_reset(void) +void do_cpu_reset(void) { - reset_prepare(); /* Sends INIT# to CPU */ outb(RST_CPU, RST_CNT); - while (1) - hlt(); } diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c index fd38f61..e38a2e6 100644 --- a/src/soc/intel/fsp_baytrail/reset.c +++ b/src/soc/intel/fsp_baytrail/reset.c @@ -29,13 +29,13 @@ outb(RST_CPU | SYS_RST, RST_CNT); } -void soft_reset(void) +void do_soft_reset(void) { /* Sends INIT# to CPU */ outb(RST_CPU, RST_CNT); } -void hard_reset(void) +void do_hard_reset(void) { /* Don't power cycle on hard_reset(). It's not really clear what the * semantics should be for the meaning of hard_reset(). */ diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c index 7e1c582..78d7493 100644 --- a/src/soc/intel/fsp_broadwell_de/reset.c +++ b/src/soc/intel/fsp_broadwell_de/reset.c @@ -23,7 +23,7 @@ outb(0x06, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { warm_reset(); } diff --git a/src/soc/intel/sch/reset.c b/src/soc/intel/sch/reset.c index 2574565..91bcd69 100644 --- a/src/soc/intel/sch/reset.c +++ b/src/soc/intel/sch/reset.c @@ -17,12 +17,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x02, 0xcf9); outb(0x06, 0xcf9); diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 6910914..dee98a4 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -41,7 +41,7 @@ hard_reset(); } -void global_reset(void) +void do_global_reset(void) { if (send_global_reset() != 0) { /* If ME unable to reset platform then diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c index 93ffe09..22f1c87 100644 --- a/src/soc/mediatek/mt8173/wdt.c +++ b/src/soc/mediatek/mt8173/wdt.c @@ -57,10 +57,7 @@ return wdt_sta; } -void hard_reset(void) +void do_hard_reset(void) { write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); - - while (1) - ; } diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index f27650d..de99a82 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -39,7 +39,7 @@ setbits_le32(&exynos_power->sw_reset, 1); } -void hard_reset(void) +void do_hard_reset(void) { power_reset(); } diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 200ec14..e3f36f3 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -21,7 +21,7 @@ #include <northbridge/amd/amdk8/reset_test.c> -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index f451003..2161669 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -38,7 +38,7 @@ enable_cf9_x(sbbusn, sbdn); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* reset */ @@ -71,7 +71,7 @@ } -void soft_reset(void) +void do_soft_reset(void) { unsigned sblk = get_sblk(); diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index fd2c82a..fea8891 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -37,7 +37,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { pci_devfn_t dev; unsigned bus; diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index a5c42b7..40e861c 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -40,7 +40,7 @@ } } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ @@ -50,7 +50,7 @@ } //SbReset(); -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index a5c42b7..40e861c 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -40,7 +40,7 @@ } } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ @@ -50,7 +50,7 @@ } //SbReset(); -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index a5c42b7..40e861c 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -40,7 +40,7 @@ } } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ @@ -50,7 +50,7 @@ } //SbReset(); -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index 200ec14..e3f36f3 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -21,7 +21,7 @@ #include <northbridge/amd/amdk8/reset_test.c> -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 2445310..f68bfd5 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -173,7 +173,7 @@ } } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -182,7 +182,7 @@ outb(0x0e, 0x0cf9); } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index beb35d1..04bf3f4 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -21,7 +21,7 @@ #include <northbridge/amd/amdk8/reset_test.c> -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 3c44982..0878039 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -44,7 +44,7 @@ } } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -56,7 +56,7 @@ outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 7ac6ec8..33422d9 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -220,7 +220,7 @@ pmio_write(0x81, byte); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -229,7 +229,7 @@ outb(0x0e, 0x0cf9); } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index 200ec14..e3f36f3 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -21,7 +21,7 @@ #include <northbridge/amd/amdk8/reset_test.c> -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 6ee4f6b..7235444 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -105,7 +105,7 @@ } -void hard_reset(void) +void do_hard_reset(void) { bcm5785_enable_wdt_port_cf9(); @@ -116,7 +116,7 @@ outb(0x0e, 0x0cf9); } -void soft_reset(void) +void do_soft_reset(void) { bcm5785_enable_wdt_port_cf9(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 7511d29..1041aae 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -21,7 +21,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 804fb81..7faadb6 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -17,12 +17,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c index a2e8236..b1468da 100644 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ b/src/southbridge/intel/fsp_bd82x6x/reset.c @@ -18,12 +18,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c index a2e8236..b1468da 100644 --- a/src/southbridge/intel/fsp_i89xx/reset.c +++ b/src/southbridge/intel/fsp_i89xx/reset.c @@ -18,12 +18,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c index 298dbce..10b82ff 100644 --- a/src/southbridge/intel/fsp_rangeley/reset.c +++ b/src/southbridge/intel/fsp_rangeley/reset.c @@ -18,12 +18,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { hard_reset(); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x02, 0xcf9); outb(0x06, 0xcf9); diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c index 595bed3..af000e3 100644 --- a/src/southbridge/intel/i3100/reset.c +++ b/src/southbridge/intel/i3100/reset.c @@ -17,7 +17,7 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/i82801ax/reset.c b/src/southbridge/intel/i82801ax/reset.c index 74be595..25254ca 100644 --- a/src/southbridge/intel/i82801ax/reset.c +++ b/src/southbridge/intel/i82801ax/reset.c @@ -17,7 +17,7 @@ #include <reset.h> #include <arch/io.h> -void hard_reset(void) +void do_hard_reset(void) { /* Try rebooting through port 0xcf9. */ outb((1 << 2) | (1 << 1), 0xcf9); diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c index 4a82b35..41b99c7 100644 --- a/src/southbridge/intel/i82801bx/reset.c +++ b/src/southbridge/intel/i82801bx/reset.c @@ -17,7 +17,7 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { /* Try rebooting through port 0xcf9. */ outb((1 << 2) | (1 << 1), 0xcf9); diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c index a6db91c..1839ad6 100644 --- a/src/southbridge/intel/i82801dx/reset.c +++ b/src/southbridge/intel/i82801dx/reset.c @@ -16,7 +16,7 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { /* Try rebooting through port 0xcf9 */ outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c index 8036ffd..10ba4ba 100644 --- a/src/southbridge/intel/i82801ex/reset.c +++ b/src/southbridge/intel/i82801ex/reset.c @@ -1,7 +1,7 @@ #include <arch/io.h> #include <reset.h> -void hard_reset(void) +void do_hard_reset(void) { /* Try rebooting through port 0xcf9 */ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c index 97b8225..e18f3e8 100644 --- a/src/southbridge/intel/i82801gx/reset.c +++ b/src/southbridge/intel/i82801gx/reset.c @@ -17,20 +17,20 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } #if 0 -void hard_reset(void) +void do_hard_reset(void) { /* Try rebooting through port 0xcf9. */ outb((1 << 2) | (1 << 1), 0xcf9); } #endif -void hard_reset(void) +void do_hard_reset(void) { outb(0x02, 0xcf9); outb(0x06, 0xcf9); diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c index 804fb81..7faadb6 100644 --- a/src/southbridge/intel/lynxpoint/reset.c +++ b/src/southbridge/intel/lynxpoint/reset.c @@ -17,12 +17,12 @@ #include <arch/io.h> #include <reset.h> -void soft_reset(void) +void do_soft_reset(void) { outb(0x04, 0xcf9); } -void hard_reset(void) +void do_hard_reset(void) { outb(0x06, 0xcf9); } diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 1d4999c..79c9eff 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -310,7 +310,7 @@ return set_ht_link_ck804(4); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -319,7 +319,7 @@ outb(0x0e, 0x0cf9); } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 689f989..aeea41b 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -357,7 +357,7 @@ return set_ht_link_ck804(4); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -366,7 +366,7 @@ outb(0x0e, 0x0cf9); } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index ad994de..bcb6dfc 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -21,7 +21,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9. */ diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 1f80316..cb3e2f0 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -25,7 +25,7 @@ #endif #include "mcp55.h" -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); /* link reset */ @@ -33,7 +33,7 @@ outb(0x06, 0x0cf9); } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index a381cd3..7be98d7 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -24,7 +24,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 74ae1fa..4fb2d9d 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -29,7 +29,7 @@ return (dev>>15) & 0x1f; } -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); @@ -44,7 +44,7 @@ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ } -void soft_reset(void) +void do_soft_reset(void) { set_bios_reset(); diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index a381cd3..7be98d7 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -24,7 +24,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void hard_reset(void) +void do_hard_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ -- To view, visit https://review.coreboot.org/19789 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: arch: Unify basic cache clearing API
by Julius Werner (Code Review) 18 May '17

18 May '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19788 to review the following change. Change subject: arch: Unify basic cache clearing API ...................................................................... arch: Unify basic cache clearing API Caching is a very architecture-specific thing, but most architectures have a cache in general. Therefore it can be useful to have a generic architecture-independent API to perform simple cache management tasks from common code. We have already standardized on the dcache_clean/invalidate naming scheme that originally comes from ARM in libpayload, so let's just do the same for coreboot. Unlike libpayload, there are other things than just DMA coherency we may want to achieve with those functions, so actually implement them for real even on architectures with cache-snooping DMA like x86. (In the future, we may find applications like this in libpayload as well and should probably rethink the API there... maybe move the current functionality to a separate dma_map/unmap API instead. But that's beyond scope of this patch.) Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/mips/include/arch/cache.h A src/arch/power8/include/arch/cache.h A src/arch/riscv/include/arch/cache.h M src/arch/x86/include/arch/cache.h 4 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/19788/1 diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index de1209a..d90a85f 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -41,4 +41,11 @@ /* Invalidate all caches: instruction, data, L2 data */ void cache_invalidate_all(uintptr_t start, size_t size); +/* TODO: Global cache API. Implement properly once we finally have a MIPS board + again where we can figure out what exactly these should be doing. */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + #endif /* __MIPS_ARCH_CACHE_H */ diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/power8/include/arch/cache.h new file mode 100644 index 0000000..9b91ac2 --- /dev/null +++ b/src/arch/power8/include/arch/cache.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef ARCH_CACHE_H +#define ARCH_CACHE_H + +/* TODO: implement these API stubs once caching is available on Power 8 */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + +#endif /* ARCH_CACHE_H */ diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h new file mode 100644 index 0000000..ba7c33d --- /dev/null +++ b/src/arch/riscv/include/arch/cache.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef ARCH_CACHE_H +#define ARCH_CACHE_H + +/* TODO: implement these API stubs once caching is available on RISC-V */ +static inline void cache_sync_instructions(void) {} +static inline void dcache_clean_all(void) {} +static inline void dcache_invalidate_all(void) {} +static inline void dcache_clean_invalidate_all(void) {} + +#endif /* ARCH_CACHE_H */ diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h index 687d3bf..e614826 100644 --- a/src/arch/x86/include/arch/cache.h +++ b/src/arch/x86/include/arch/cache.h @@ -31,6 +31,9 @@ #ifndef ARCH_CACHE_H #define ARCH_CACHE_H +#include <arch/early_variables.h> +#include <cpu/x86/cache.h> + /* * For the purposes of the currently executing CPU loading code that will be * run there aren't any cache coherency operations required. This just provides @@ -38,4 +41,22 @@ */ static inline void cache_sync_instructions(void) {} +/* I'm not sure what a WBINVD would do when running out of CAR, but probably + not what arch-independent code would expect, so exclude that case. */ +static inline void dcache_clean_all(void) +{ + if (!car_active()) + wbinvd(); /* can't "clean without invalidate" on x86 */ +} +static inline void dcache_invalidate_all(void) +{ + if (!car_active()) + invd(); +} +static inline void dcache_clean_invalidate_all(void) +{ + if (!car_active()) + wbinvd(); +} + #endif /* ARCH_CACHE_H */ -- To view, visit https://review.coreboot.org/19788 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: arch/x86: Add function to determine if we're currently runni...
by Julius Werner (Code Review) 18 May '17

18 May '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19787 to review the following change. Change subject: arch/x86: Add function to determine if we're currently running from CAR ...................................................................... arch/x86: Add function to determine if we're currently running from CAR This patch adds a simple function that can be used to check if CAR_GLOBALs are currently being read from CAR or from DRAM. Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/include/arch/early_variables.h M src/cpu/x86/car.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/19787/1 diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index d0cfda7..2c6c539 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -44,12 +44,20 @@ { return var; } + +static inline int car_active(void) +{ + return 1; +} #else /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); /* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ void *car_sync_var_ptr(void *var); + +/* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ +int car_active(void); #endif /* ENV_VERSTAGE */ /* Get and set a primitive type global variable. */ @@ -73,6 +81,7 @@ #else #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } +static inline int car_active(void) { return 0; } #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 606a35e..cd3fb35 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -113,6 +113,11 @@ return mig_var; } +int car_active(void) +{ + return !!car_migrated; +} + static void do_car_migrate_variables(void) { void *migrated_base; -- To view, visit https://review.coreboot.org/19787 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: tegra210: Remove fake cpu_reset()
by Julius Werner (Code Review) 18 May '17

18 May '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19786 to review the following change. Change subject: tegra210: Remove fake cpu_reset() ...................................................................... tegra210: Remove fake cpu_reset() The Tegra210 SoC never had a proper cpu_reset() implementation, so it's pointless to pretend there is one. Most ARM SoCs/boards only define hard_reset() at the moment anyway, so let's stick with that. Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/soc/nvidia/tegra210/Makefile.inc D src/soc/nvidia/tegra210/reset.c 4 files changed, 4 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19786/1 diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 2e655b5..2eeccb2 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -43,8 +43,8 @@ if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); + /* Reset the board on any PMIC write error */ + hard_reset(); } else { if (delay) udelay(500); diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index cba555a..25e870a 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -46,8 +46,8 @@ if (i2c_writeb(bus, chip, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); - /* Reset the SoC on any PMIC write error */ - cpu_reset(); + /* Reset the board on any PMIC write error */ + hard_reset(); } else { if (delay) udelay(500); diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 756d413..a2b50c9 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -12,7 +12,6 @@ bootblock-y += padconfig.c bootblock-y += power.c bootblock-y += funitcfg.c -bootblock-y += reset.c bootblock-y += ../tegra/gpio.c bootblock-y += ../tegra/i2c.c bootblock-y += ../tegra/pingroup.c @@ -41,7 +40,6 @@ romstage-y += ccplex.c romstage-y += clock.c romstage-y += cpu.c -romstage-y += reset.c romstage-y += spi.c romstage-y += i2c.c romstage-y += dma.c @@ -87,7 +85,6 @@ ramstage-y += monotonic_timer.c ramstage-y += padconfig.c ramstage-y += funitcfg.c -ramstage-y += reset.c ramstage-y += ram_code.c ramstage-y += ../tegra/apbmisc.c ramstage-y += ../tegra/gpio.c diff --git a/src/soc/nvidia/tegra210/reset.c b/src/soc/nvidia/tegra210/reset.c deleted file mode 100644 index 38a97d8..0000000 --- a/src/soc/nvidia/tegra210/reset.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -/* - * Promote cpu_reset() to a hard_reset(). A shallower reset can be added, - * if needed, at a later time. - */ -void cpu_reset(void) -{ - hard_reset(); -} -- To view, visit https://review.coreboot.org/19786 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: arm64: Align cache maintenance code with libpayload and ARM32
by Julius Werner (Code Review) 18 May '17

18 May '17

Hello Aaron Durbin, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/19785 to review the following change. Change subject: arm64: Align cache maintenance code with libpayload and ARM32 ...................................................................... arm64: Align cache maintenance code with libpayload and ARM32 coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/arm64/cache.c M src/arch/arm64/armv8/Makefile.inc M src/arch/arm64/armv8/cache.c D src/arch/arm64/armv8/cache_helpers.S M src/arch/arm64/armv8/cpu.S M src/arch/arm64/armv8/mmu.c D src/arch/arm64/include/arch/cache_helpers.h M src/arch/arm64/include/armv8/arch/cache.h 8 files changed, 93 insertions(+), 194 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/19785/1 diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 0755c56..2d42522 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -119,7 +119,11 @@ void cache_sync_instructions(void) { - dcache_clean_all(); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index a7a6b19..21ebf70 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -28,7 +28,6 @@ bootblock-y += bootblock.S endif bootblock-y += cache.c -bootblock-y += cache_helpers.S bootblock-y += cpu.S bootblock-y += mmu.c @@ -50,7 +49,6 @@ verstage-y += cache.c verstage-y += cpu.S -verstage-y += cache_helpers.S verstage-y += exception.c verstage-generic-ccopts += $(armv8_flags) @@ -63,7 +61,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c -romstage-y += cache_helpers.S romstage-y += cpu.S romstage-y += exception.c romstage-y += mmu.c @@ -80,7 +77,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c -ramstage-y += cache_helpers.S ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += mmu.c diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 4f91de0..4b99cd7 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -34,7 +34,6 @@ #include <stdint.h> #include <arch/cache.h> -#include <arch/cache_helpers.h> #include <arch/lib_helpers.h> #include <program_loading.h> @@ -121,7 +120,11 @@ void cache_sync_instructions(void) { - flush_dcache_all(DCCISW); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ } @@ -131,6 +134,10 @@ */ void arch_segment_loaded(uintptr_t start, size_t size, int flags) { - dcache_clean_invalidate_by_mva((void *)start, size); + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_by_mva((void *)start, size); + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_by_mva((void *)start, size); icache_invalidate_all(); } diff --git a/src/arch/arm64/armv8/cache_helpers.S b/src/arch/arm64/armv8/cache_helpers.S deleted file mode 100644 index b94bc30..0000000 --- a/src/arch/arm64/armv8/cache_helpers.S +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch/asm.h> -#include <arch/cache_helpers.h> - - /* --------------------------------------------------------------- - * Data cache operations by set/way to the level specified - * - * The main function, do_dcsw_op requires: - * x0: The operation type (0-2), as defined in cache_helpers.h - * x3: The last cache level to operate on - * x9: clidr_el1 - * and will carry out the operation on each data cache from level 0 - * to the level in x3 in sequence - * - * The dcsw_op macro sets up the x3 and x9 parameters based on - * clidr_el1 cache information before invoking the main function - * --------------------------------------------------------------- - */ - -.macro dcsw_op shift, fw, ls - mrs x9, clidr_el1 - ubfx x3, x9, \shift, \fw - lsl x3, x3, \ls - b do_dcsw_op -.endm - -ENTRY(do_dcsw_op) - cbz x3, exit - mov x10, xzr - adr x14, dcsw_loop_table // compute inner loop address - add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions - mov x0, x9 - mov w8, #1 -loop1: - add x2, x10, x10, lsr #1 // work out 3x current cache level - lsr x1, x0, x2 // extract cache type bits from clidr - and x1, x1, #7 // mask the bits for current cache only - cmp x1, #2 // see what cache we have at this level - b.lt level_done // nothing to do if no cache or icache - - msr csselr_el1, x10 // select current cache level in csselr - isb // isb to sych the new cssr&csidr - mrs x1, ccsidr_el1 // read the new ccsidr - and x2, x1, #7 // extract the length of the cache lines - add x2, x2, #4 // add 4 (line length offset) - ubfx x4, x1, #3, #10 // maximum way number - clz w5, w4 // bit position of way size increment - lsl w9, w4, w5 // w9 = aligned max way number - lsl w16, w8, w5 // w16 = way number loop decrement - orr w9, w10, w9 // w9 = combine way and cache number - ubfx w6, w1, #13, #15 // w6 = max set number - lsl w17, w8, w2 // w17 = set number loop decrement - dsb sy // barrier before we start this level - br x14 // jump to DC operation specific loop - -level_done: - add x10, x10, #2 // increment cache number - cmp x3, x10 - b.gt loop1 - msr csselr_el1, xzr // select cache level 0 in csselr - dsb sy // barrier to complete final cache operation - isb -exit: - ret -ENDPROC(do_dcsw_op) - -.macro dcsw_loop _op -loop2_\_op: - lsl w7, w6, w2 // w7 = aligned max set number - -loop3_\_op: - orr w11, w9, w7 // combine cache, way and set number - dc \_op, x11 - subs w7, w7, w17 // decrement set number - b.ge loop3_\_op - - subs x9, x9, x16 // decrement way number - b.ge loop2_\_op - - b level_done -.endm - -dcsw_loop_table: - dcsw_loop isw - dcsw_loop cisw - dcsw_loop csw - -ENTRY(flush_dcache_louis) - dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT -ENDPROC(flush_dcache_louis) - -ENTRY(flush_dcache_all) - dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT -ENDPROC(flush_dcache_all) diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index 711c338..1bb8c83 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -1,8 +1,8 @@ /* - * Based on arch/arm/include/asm/cacheflush.h + * Optimized assembly for low-level CPU operations on ARM64 processors. * - * Copyright (C) 1999-2002 Russell King. - * Copyright (C) 2012 ARM Ltd. + * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> + * Copyright (c) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,11 +15,77 @@ */ #include <arch/asm.h> -#include <arch/cache_helpers.h> + +.macro dcache_apply_all crm + dsb sy + mrs x0, clidr_el1 // read CLIDR + and w3, w0, #0x07000000 // narrow to LoC + lsr w3, w3, #23 // left align LoC (low 4 bits) + cbz w3, 5f //done + + mov w10, #0 // w10 = 2 * cache level + mov w8, #1 // w8 = constant 0b1 + +1: //next_level + add w2, w10, w10, lsr #1 // calculate 3 * cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 // w1 = cache type + cmp w1, #2 // is it data or i&d? + b.lt 4f //skip + msr csselr_el1, x10 // select current cache level + isb // sync change of csselr + mrs x1, ccsidr_el1 // w1 = read ccsidr + and w2, w1, #7 // w2 = log2(linelen_bytes) - 4 + add w2, w2, #4 // w2 = log2(linelen_bytes) + ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also + // max way number) + clz w5, w4 // w5 = 32 - log2(ways) + // (bit position of way in DC) + lsl w9, w4, w5 // w9 = max way number + // (aligned for DC) + lsl w16, w8, w5 // w16 = amount to decrement (way + // number per iteration) +2: //next_way + ubfx w7, w1, #13, #15 // w7 = max set #, right aligned + lsl w7, w7, w2 // w7 = max set #, DC aligned + lsl w17, w8, w2 // w17 = amount to decrement (set + // number per iteration) + +3: //next_set + orr w11, w10, w9 // w11 = combine way # & cache # + orr w11, w11, w7 // ... and set # + dc \crm, x11 // clean and/or invalidate line + subs w7, w7, w17 // decrement set number + b.ge 3b //next_set + subs x9, x9, x16 // decrement way number + b.ge 2b //next_way + +4: //skip + add w10, w10, #2 // increment 2 *cache level + cmp w3, w10 // Went beyond LoC? + b.gt 1b //next_level + +5: //done + dsb sy + isb + ret +.endm + +ENTRY(dcache_invalidate_all) + dcache_apply_all crm=isw +ENDPROC(dcache_invalidate_all) + +ENTRY(dcache_clean_all) + dcache_apply_all crm=csw +ENDPROC(dcache_clean_all) + +ENTRY(dcache_clean_invalidate_all) + dcache_apply_all crm=cisw +ENDPROC(dcache_clean_invalidate_all) /* * Bring an ARMv8 processor we just gained control of (e.g. from IROM) into a - * known state regarding caches/SCTLR/PSTATE. Completely cleans and invalidates + * known state regarding caches/SCTLR/PSTATE. Completely invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned * accesses, icache and branch prediction (if inactive). Seeds the stack and * initializes SP_EL0. Clobbers R22 and R23. @@ -41,9 +107,8 @@ msr sctlr_el3, x22 isb - /* Flush and invalidate dcache */ - mov x0, #DCCISW - bl flush_dcache_all + /* Invalidate dcache */ + bl dcache_invalidate_all /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */ and x22, x22, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2) diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 9280fc2..55bd703 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -37,7 +37,6 @@ #include <arch/mmu.h> #include <arch/lib_helpers.h> #include <arch/cache.h> -#include <arch/cache_helpers.h> /* This just caches the next free table slot (okay to do since they fill up from * bottom to top and can never be freed up again). It will reset to its initial @@ -295,7 +294,7 @@ */ void mmu_disable(void) { - flush_dcache_all(DCCISW); + dcache_clean_invalidate_all(); uint32_t sctlr = raw_read_sctlr_el3(); sctlr &= ~(SCTLR_C | SCTLR_M); raw_write_sctlr_el3(sctlr); diff --git a/src/arch/arm64/include/arch/cache_helpers.h b/src/arch/arm64/include/arch/cache_helpers.h deleted file mode 100644 index 2919d99..0000000 --- a/src/arch/arm64/include/arch/cache_helpers.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CACHE_HELPERS_H - -/* CLIDR definitions */ -#define LOUIS_SHIFT 21 -#define LOC_SHIFT 24 -#define CLIDR_FIELD_WIDTH 3 - -/* CSSELR definitions */ -#define LEVEL_SHIFT 1 - -/* D$ set/way op type defines */ -#define DCISW 0x0 -#define DCCISW 0x1 -#define DCCSW 0x2 - -#endif /* __CACHE_HELPERS_H */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 84f051d..3647290 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -67,11 +67,10 @@ /* dcache invalidate by virtual address to PoC */ void dcache_invalidate_by_mva(void const *addr, size_t len); -/* dcache invalidate all */ -void flush_dcache_all(int op_type); - -/* flush the dcache up to the Level of Unification Inner Shareable */ -void flush_dcache_louis(int op_type); +/* dcache clean and/or invalidate all sets/ways to PoC */ +void dcache_clean_all(void); +void dcache_invalidate_all(void); +void dcache_clean_invalidate_all(void); /* returns number of bytes per cache line */ unsigned int dcache_line_bytes(void); -- To view, visit https://review.coreboot.org/19785 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit May 2017