coreboot-gerrit May 2017

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Change in coreboot[master]: mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447Hz
by Arthur Heymans (Code Review) 22 May '17

22 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19816 ) Change subject: mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447Hz ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy: Update SPD data
by Furquan Shaikh (Code Review) 22 May '17

22 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19692 ) Change subject: mb/google/poppy: Update SPD data ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19692/3/src/mainboard/google/poppy/spd/hyni… File src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex: PS3, Line 10: 54 This should be 55. Rest all looks good. -- To view, visit https://review.coreboot.org/19692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/sandybridge/pcie: Disable unused bridges
by Patrick Rudolph (Code Review) 22 May '17

22 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19819 ) Change subject: nb/intel/sandybridge/pcie: Disable unused bridges ...................................................................... nb/intel/sandybridge/pcie: Disable unused bridges Add a PCI Express Root Port driver. Disable unused bridges that are not hot-plug capable. Reduces idle power by ~1 Watt, as the PEG slot gets disabled. Tested on Lenovo T430. Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 82 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19819/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a40fa15..88c4fb1 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c +ramstage-y += pcie.c ramstage-y += gma.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c new file mode 100644 index 0000000..98b5764 --- /dev/null +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <southbridge/intel/common/pciehp.h> +#include "sandybridge.h" + +static void pcie_scan_bridge(device_t dev) +{ + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); + + /* Hotplug capable ? */ + if (pci_read_config32(dev, SLOTCAP) & (1 << 6)) + return; + + if (!dev_is_active_bridge(dev)) + dev->ops->disable(dev); +} + +static void pcie_disable(device_t dev) +{ + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); + + dev->enabled = 0; +} + +static void +pcie_set_subsystem(device_t dev, unsigned int vendor, unsigned int device) +{ + /* NOTE: This is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + } else { + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .disable = pcie_disable, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d, + 0x0151, 0x0155, 0x0159, 0x015d, + 0 }; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index bc659be..8545d7f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -109,7 +109,7 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ - +#define SLOTCAP 0xb4 /* Slot Capabilities Register */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- To view, visit https://review.coreboot.org/19819 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If67bafdea6a60986ecca2ecdb93c7f72359c4537 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Disable unused bridges
by Patrick Rudolph (Code Review) 22 May '17

22 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19818 ) Change subject: sb/intel/bd82x6x: Disable unused bridges ...................................................................... sb/intel/bd82x6x: Disable unused bridges Disable unused bridges that are not marked as hot-plugable. Should reduce power consumption. Tested on Lenovo T430. Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/19818/1 diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 91add02..627b6f7 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -269,6 +269,14 @@ pch_pcie_pm_early(dev); } +static void pch_pcie_disable(device_t dev) +{ + dev->enabled = 0; + + /* Let PCH hide the device */ + pch_enable(dev); +} + static void pch_pciexp_scan_bridge(device_t dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; @@ -278,6 +286,11 @@ if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + } else { + if (!dev_is_active_bridge(dev)) { + dev->ops->disable(dev); + return; + } } /* Late Power Management init after bridge device enumeration */ @@ -305,6 +318,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, + .disable = pch_pcie_disable, .enable = pch_pcie_enable, .scan_bus = pch_pciexp_scan_bridge, .ops_pci = &pci_ops, -- To view, visit https://review.coreboot.org/19818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: device/device_util: Add function to determine bridge state
by Patrick Rudolph (Code Review) 22 May '17

22 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19817 ) Change subject: device/device_util: Add function to determine bridge state ...................................................................... device/device_util: Add function to determine bridge state Add a method to get the state of a bridge device. Recursively scan all buses behind the bridge for enabled devices. Return true if at least one enabled device is found. Useful to disable non hotplugable bridges without any devices attached. Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/device/device_util.c M src/include/device/device.h 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19817/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index e31ade5..2e59a11 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -775,6 +775,35 @@ } } +/* + * Returns true if the device is an enabled bridge that has at least + * one enabled device on it's secondary bus or behind further + * bridge devices. + */ +bool dev_is_active_bridge(device_t dev) +{ + struct bus *link; + device_t child; + + if (!dev || !dev->enabled) + return 0; + + if (!dev->link_list || !dev->link_list->children) + return 0; + + for (link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (!child->link_list && child->enabled) + return 1; + + if (dev_is_active_bridge(child)) + return 1; + } + } + + return 0; +} + static void resource_tree(struct device *root, int debug_level, int depth) { int i = 0; diff --git a/src/include/device/device.h b/src/include/device/device.h index 7b4fce3..5bc4d1c 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -190,6 +190,7 @@ const char *bus_path(struct bus *bus); void dev_set_enabled(device_t dev, int enable); void disable_children(struct bus *bus); +bool dev_is_active_bridge(device_t dev); /* Option ROM helper functions */ void run_bios(struct device *dev, unsigned long addr); -- To view, visit https://review.coreboot.org/19817 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447Hz
by build bot (Jenkins) (Code Review) 22 May '17

22 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19816 ) Change subject: mb/lenovo/x200/blc: Add LTD121EQ3B panel at 447Hz ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9878/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54143/ : SUCCESS -- To view, visit https://review.coreboot.org/19816 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia44097f32f74ffd749219415984224ce33d9252b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add entry for deep Sx wake
by Furquan Shaikh (Code Review) 22 May '17

22 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19798 ) Change subject: soc/intel/skylake: Add entry for deep Sx wake ...................................................................... soc/intel/skylake: Add entry for deep Sx wake If deep Sx is enabled and prev sleep state was not S0, then if SUS power was lost, it means that the platform had entered deep Sx. Add an elog entry for deep Sx variant in this case. BUG=b:38436041 TEST=Verified that elog entries are updated correctly: Deep S5: 59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown 60 | 2017-05-19 10:39:09 | ACPI Enter | S5 61 | 2017-05-19 10:39:17 | System boot | 22 62 | 2017-05-19 10:39:17 | EC Event | Power Button 63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5 64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0 65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode Deep S3: 66 | 2017-05-19 10:40:11 | ACPI Enter | S3 67 | 2017-05-19 10:40:16 | EC Event | Power Button 68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3 69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0 Normal S3: 77 | 2017-05-19 10:43:22 | ACPI Enter | S3 78 | 2017-05-19 10:43:39 | EC Event | Power Button 79 | 2017-05-19 10:43:39 | ACPI Wake | S3 80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0 Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19798 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/skylake/elog.c 1 file changed, 20 insertions(+), 4 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 562df08..6db15f5 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -70,6 +70,17 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps) { + bool deep_sx; + + /* + * Platform entered deep Sx if: + * 1. Prev sleep state was Sx and deep_sx_enabled() is true + * 2. SUS well power was lost + */ + deep_sx = ((((ps->prev_sleep_state == ACPI_S3) && deep_s3_enabled()) || + ((ps->prev_sleep_state == ACPI_S5) && deep_s5_enabled())) && + (ps->gen_pmcon_b & SUS_PWR_FLR)); + /* Thermal Trip */ if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP) elog_add_event(ELOG_TYPE_THERM_TRIP); @@ -81,8 +92,7 @@ /* SUS Well Power Failure */ if (ps->gen_pmcon_b & SUS_PWR_FLR) { /* Do not log SUS_PWR_FLR if waking from deep Sx */ - if (!(ps->prev_sleep_state == ACPI_S3 && deep_s3_enabled()) && - !(ps->prev_sleep_state == ACPI_S5 && deep_s5_enabled())) + if (!deep_sx) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); } @@ -104,8 +114,14 @@ elog_add_event(ELOG_TYPE_SYSTEM_RESET); /* ACPI Wake Event */ - if (ps->prev_sleep_state != ACPI_S0) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); + if (ps->prev_sleep_state != ACPI_S0) { + if (deep_sx) + elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE, + ps->prev_sleep_state); + else + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + ps->prev_sleep_state); + } } static void pch_log_state(void *unused) -- To view, visit https://review.coreboot.org/19798 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: elog: Add a new elog type for deep Sx variant
by Furquan Shaikh (Code Review) 22 May '17

22 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19797 ) Change subject: elog: Add a new elog type for deep Sx variant ...................................................................... elog: Add a new elog type for deep Sx variant This is useful for debugging based on eventlog to identify if platform entered normal or deep Sx. BUG=b:38436041 Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19797 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/include/elog.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/elog.h b/src/include/elog.h index 964e040..f18aa4b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -113,6 +113,7 @@ /* Sleep/Wake */ #define ELOG_TYPE_ACPI_ENTER 0x9d +/* Deep Sx wake variant is provided below - 0xad */ #define ELOG_TYPE_ACPI_WAKE 0x9e #define ELOG_TYPE_WAKE_SOURCE 0x9f #define ELOG_WAKE_SOURCE_PCIE 0x00 @@ -178,6 +179,9 @@ /* Cr50 */ #define ELOG_TYPE_CR50_UPDATE 0xac +/* Deep Sx wake variant */ +#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); -- To view, visit https://review.coreboot.org/19797 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ic7d8e5b8aafc07aed385fe3c4831ab7d29e1f890 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: include/device: Add pci ids for Intel GLK
by build bot (Jenkins) (Code Review) 22 May '17

22 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19686 ) Change subject: include/device: Add pci ids for Intel GLK ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9877/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54142/ : SUCCESS -- To view, visit https://review.coreboot.org/19686 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifbca20a0c38cc1fb8ee4b4e336d59e834fcaf57a Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common CPU code
by build bot (Jenkins) (Code Review) 22 May '17

22 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: [WIP]Add Intel common CPU code ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54141/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9876/ : SUCCESS -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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coreboot-gerrit May 2017