coreboot-gerrit April 2017

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Change in coreboot[master]: util/inteltool: Break long lines in supported_chips_list
by Martin Roth (Code Review) 01 May '17

01 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19444 ) Change subject: util/inteltool: Break long lines in supported_chips_list ...................................................................... util/inteltool: Break long lines in supported_chips_list Lint prevents my next commit which adds a new line to the table so it's better to break all the > 80 character lines so it will be consistent with the new line I'm about to add. Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/19444 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/inteltool/inteltool.c 1 file changed, 50 insertions(+), 25 deletions(-) Approvals: Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 79b0bce..a4814f8 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -61,35 +61,55 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X, + "GL40/GS40/GM45/GS45/PM45" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q45, "Q45/Q43" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G45, "G45/G43/P45/P43" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G41, "G41" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43, "B43 (Base)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43_2, "B43 (Soft)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, + "Intel i5000P Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, + "Intel i5000X Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, + "Intel i5000Z Memory Controller Hub" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, + "Intel i5000V Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, + "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, /* Host bridges /DRAM controllers integrated in CPUs */ - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, "2nd generation (Sandy Bridge family) Core Processor (Desktop)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M, "2nd generation (Sandy Bridge family) Core Processor (Mobile)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3, "2nd generation (Sandy Bridge family) Core Processor (Xeon E3)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, "3rd generation (Ivy Bridge family) Core Processor (Desktop)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M, "3rd generation (Ivy Bridge family) Core Processor (Mobile)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3, "3rd generation (Ivy Bridge family) Core Processor (Xeon E3 v2)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c, "3rd generation (Ivy Bridge family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D, "4th generation (Haswell family) Core Processor (Desktop)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, + "0th generation (Nehalem family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, + "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, + "2nd generation (Sandy Bridge family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M, + "2nd generation (Sandy Bridge family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3, + "2nd generation (Sandy Bridge family) Core Processor (Xeon E3)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D, + "3rd generation (Ivy Bridge family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M, + "3rd generation (Ivy Bridge family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3, + "3rd generation (Ivy Bridge family) Core Processor (Xeon E3 v2)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c, + "3rd generation (Ivy Bridge family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D, + "4th generation (Haswell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, + "4th generation (Haswell family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, + "4th generation (Haswell family) Core Processor (Xeon E3 v3)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, + "4th generation (Haswell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, + "5th generation (Broadwell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, @@ -128,7 +148,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM55, "HM55" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q57, "Q57" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM57, "HM57" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF, "3400 Mobile SFF" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF, + "3400 Mobile SFF" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B55_A, "B55" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS57, "QS57" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3400, "3400" }, @@ -167,10 +188,14 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, "Wildcat Point Low Power SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, + "Lynx Point Low Power Full Featured Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, + "Lynx Point Low Power Premium SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, + "Lynx Point Low Power Base SKU" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, + "Wildcat Point Low Power SKU" }, { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, }; -- To view, visit https://review.coreboot.org/19444 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: util/inteltool: Break long lines in supported_chips_list
by Martin Roth (Code Review) 01 May '17

01 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19444 ) Change subject: util/inteltool: Break long lines in supported_chips_list ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19444 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: acpi: fix FADT header version for ChromeOS devices
by Martin Roth (Code Review) 01 May '17

01 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19498 ) Change subject: acpi: fix FADT header version for ChromeOS devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19498 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 30 Apr '17

30 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 35: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/52996/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8840/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 35 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans (Code Review) 30 Apr '17

30 Apr '17

Hello build bot (Jenkins), coreboot org, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18305 to look at the new patch set (#35). Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... nb/i945/raminit: Use common ddr2 decode functions This simplifies computing dram timings a lot. This removes computation of rank size based on columns, rows, banks,... and uses the information in SPD byte 31. The result of this is that dimms with multiple asymmetric ranks are not supported anymore. These however are very rare and most likely never tested on this platform. This also uses i2c block read instead of byte read to speed up the raminit. The result is less time is being spend reading SPDs. It still keeps smbus read byte as a backup if i2c block read were to fail. Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 156 insertions(+), 614 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/18305/35 -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 35 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 30 Apr '17

30 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 34: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/52995/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/8839/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 34 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans (Code Review) 30 Apr '17

30 Apr '17

Hello build bot (Jenkins), coreboot org, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18305 to look at the new patch set (#34). Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... nb/i945/raminit: Use common ddr2 decode functions This simplifies computing dram timings a lot. This removes computation of rank size based on columns, rows, banks,... and uses the information in SPD byte 31. The result of this is that dimms with multiple asymmetric ranks are not supported anymore. These however are very rare and most likely never tested on this platform. This also uses i2c block read instead of byte read to speed up the raminit. The result is less time is being spend reading SPDs. It still keeps smbus read byte as a backup if i2c block read were to fail. Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 156 insertions(+), 614 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/18305/34 -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 34 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by build bot (Jenkins) (Code Review) 30 Apr '17

30 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19143 ) Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/52994/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8838/ : SUCCESS -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by Arthur Heymans (Code Review) 30 Apr '17

30 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19143 to look at the new patch set (#15). Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... nb/x4x/raminit: Rewrite SPD decode and timing selection This is mostly written from scratch and uses common spd ddr2 decode functions. This improves the following: * This fixes incorrect CAS/Freq detection on DDR2; * Timings selection does not use loops; * Removes ddr3 spd decode, since there is no DDR3 raminit. For this it would be nice to use similar common functions for DDR3; * Raminit would bail out if dimm was unsupported, now in some cases it just marks the dimm slot as empty; * It dramatically reduces stack usage since it does not allocate 4 times 256 bytes to store full SPDs, amongs other unused things that were stored in sysinfo. * Reports when no dimms are present. * Uses i2c block read to read SPD which is about 5 times faster than bytewise read, with a fallback to smbus mode in case of failure. TESTED: on ga-g41m-es2l. Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr2.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 294 insertions(+), 380 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/15 -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by build bot (Jenkins) (Code Review) 30 Apr '17

30 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19143 ) Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/52993/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8837/ : SUCCESS -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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coreboot-gerrit April 2017