Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), coreboot org,

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/18305

to look at the new patch set (#34).

Change subject: nb/i945/raminit: Use common ddr2 decode functions
......................................................................

nb/i945/raminit: Use common ddr2 decode functions

This simplifies computing dram timings a lot.

This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.

This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.

Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
2 files changed, 156 insertions(+), 614 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/18305/34