coreboot-gerrit March 2017

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Change in coreboot[master]: util/futility/Makefile: Update clean target
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18998 ) Change subject: util/futility/Makefile: Update clean target ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/50875/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/6851/ : SUCCESS -- To view, visit https://review.coreboot.org/18998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: util/futility/Makefile: Update clean target
by Martin Roth (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Paul Kocialkowski, Paul Menzel, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18998 to look at the new patch set (#4). Change subject: util/futility/Makefile: Update clean target ...................................................................... util/futility/Makefile: Update clean target - Fix clean target to pass if output doesn't exist - Make sure $(RM) is actually defined Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/futility/Makefile 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/18998/4 -- To view, visit https://review.coreboot.org/18998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: payloads/nvramcui/Makefile: Remove junit.xml
by Martin Roth (Code Review) 28 Mar '17

28 Mar '17

Martin Roth has abandoned this change. ( https://review.coreboot.org/18999 ) Change subject: payloads/nvramcui/Makefile: Remove junit.xml ...................................................................... Abandoned Doing it a different way. -- To view, visit https://review.coreboot.org/18999 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: abandon Gerrit-Change-Id: I9d1824e2716f4d886f68d5b43afa40c7cea150df Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: util/futility/Makefile: Update clean target
by Martin Roth (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Paul Kocialkowski, Paul Menzel, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18998 to look at the new patch set (#3). Change subject: util/futility/Makefile: Update clean target ...................................................................... util/futility/Makefile: Update clean target - Fix clean target to pass if output doesn't exist - Make sure $(RM) is actually defined - Remove junit.xml file if it was generated by what-jenkins-does Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M util/futility/Makefile 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/18998/3 -- To view, visit https://review.coreboot.org/18998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibcdb0e329084f58b27c3f53213a237d02c922a51 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: abuild: Treat command line for recursive invocations as bash...
by Martin Roth (Code Review) 28 Mar '17

28 Mar '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/18975 ) Change subject: abuild: Treat command line for recursive invocations as bash array ...................................................................... Patch Set 3: (3 comments) currently the -t "vendor1/board1 vendor2/board2", doesn't work although I think that would be a good addition. https://review.coreboot.org/#/c/18975/3/util/abuild/abuild File util/abuild/abuild: PS3, Line 19: ABUILD_DATE="Dec 6, 2016" : ABUILD_VERSION="0.10.01" Do you think this change is worth updating the version and date? PS3, Line 784: local num_targets=$(wc -w <<<$targets) >From shellcheck local num_targets=$(wc -w <<<$targets) ^-- SC2155: Declare and assign separately to avoid masking return values. ^-- SC2086: Double quote to prevent globbing and word splitting. PS3, Line 785: local cpus_per_target=$(((${cpus:-1} + $num_targets - 1) / $num_targets)) >From shellcheck: local cpus_per_target=$(((${cpus:-1} + $num_targets - 1) / $num_targets)) ^-- SC2004: $/${} is unnecessary on arithmetic variables. ^-- SC2004: $/${} is unnecessary on arithmetic variables. -- To view, visit https://review.coreboot.org/18975 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I76a1c6456ef8ab21286fdc1636d659a3b76bc5d7 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/18669/3/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/pcr_ids.h: Line 1: /* > I don't see the point of adding a header that isn't actually used. If you a yes, true, will modify -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/18669/3/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/pcr_ids.h: Line 1: /* > We have lots of things being added. But nothing being removed? If you are g initially i have created 6 patch for entire PCR, later i thought lets have only common code + 2 SOC using that common code along with clean up. If you want, i may split adding pcr_id.h first and push assessment patch for 2 SOC (APL and SKL) then add PCR library and finally using that common code -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common System A...
by Martin Roth (Code Review) 28 Mar '17

28 Mar '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18567 ) Change subject: soc/intel/apollolake: Clean up code by using common System Agent module ...................................................................... soc/intel/apollolake: Clean up code by using common System Agent module This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/18567 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c R src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/northbridge.c M src/soc/intel/apollolake/romstage.c 7 files changed, 16 insertions(+), 32 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 5087fa6..9b847da 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -41,6 +41,7 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select PCIEX_LENGTH_256MB select POSTCAR_CONSOLE select POSTCAR_STAGE select REG_SCRIPT @@ -51,6 +52,7 @@ select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT @@ -88,10 +90,6 @@ config SOC_INTEL_COMMON_RESET bool default y - -config MMCONF_BASE_ADDRESS - hex "PCI MMIO Base Address" - default 0xe0000000 config IOSF_BASE_ADDRESS hex "MMIO Base Address of sideband bus" @@ -283,7 +281,7 @@ bool "Use FSP CAR" select FSP_CAR help - Use FSP APIs to initialize & tear Down the Cache-As-Ram. + Use FSP APIs to initialize & tear down the Cache-As-Ram. endchoice diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ed4530c..dc17b15 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <intelblocks/systemagent.h> #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -25,7 +26,7 @@ #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/uart.h> @@ -51,16 +52,9 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - device_t dev = SA_DEV_ROOT; + device_t dev; - /* Set PCI Express BAR */ - pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); - /* - * Clear TSEG register - TSEG register comes out of reset with a - * non-zero default value. Clear this register to ensure that there are - * no surprises in CBMEM handling. - */ - pci_write_config32(dev, TSEG, 0); + bootblock_systemagent_early_init(); dev = PCH_DEV_P2SB; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 71706d0..8aed7b6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -37,7 +37,7 @@ #include <spi-generic.h> #include <soc/pm.h> #include <soc/p2sb.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include "chip.h" diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/systemagent.h similarity index 68% rename from src/soc/intel/apollolake/include/soc/northbridge.h rename to src/soc/intel/apollolake/include/soc/systemagent.h index 04e369e..9944c15 100644 --- a/src/soc/intel/apollolake/include/soc/northbridge.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -15,18 +15,10 @@ * GNU General Public License for more details. */ -#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ -#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ +#ifndef SOC_APOLLOLAKE_SYSTEMAGENT_H +#define SOC_APOLLOLAKE_SYSTEMAGENT_H -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define PCIEX_SIZE (256 * MiB) - -#define BDSM 0xb0 /* Base Data Stolen Memory */ -#define BGSM 0xb4 /* Base GTT Stolen Memory */ -#define TSEG 0xb8 /* TSEG base */ -#define TOLUD 0xbc /* Top of Low Used Memory */ -#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ +#include <intelblocks/systemagent.h> /* IMR registers are found under MCHBAR. */ #define MCHBAR_IMR0BASE 0x6870 @@ -37,4 +29,4 @@ /* RAPL Package Power Limit register under MCHBAR. */ #define MCHBAR_RAPL_PPL 0x70A8 -#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ +#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index a10477c..0f85b10 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -27,7 +27,7 @@ #include <assert.h> #include <cbmem.h> #include <device/pci.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/smm.h> diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 6f92283..9519603 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -20,7 +20,7 @@ #include <soc/iomap.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include <soc/pci_ids.h> static uint32_t get_bar(device_t dev, unsigned int index) @@ -39,7 +39,7 @@ /* PCI extended config region */ addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB; - mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB); + mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB); /* Memory Controller Hub */ addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 38cf81c..0270920 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -35,7 +35,7 @@ #include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -- To view, visit https://review.coreboot.org/18567 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Gerrit-PatchSet: 27 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 28 Mar '17

28 Mar '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/18557/14/src/soc/intel/common/block/fast_sp… File src/soc/intel/common/block/fast_spi/fast_spi.c: Line 39: void get_bios_rom_region(size_t *bios_start, size_t *bios_end) > Why isn't this function returning a value? You only need one parameter that The caller function will not only need the bios size, but also requires the bios_start. >>> xlate_region_device_ro_init(real_dev_ptr, &shadow_dev_ptr->rdev, start, bios_mapped_size, CONFIG_ROM_SIZE); >>> That's why I kept these two argument passing and no return parameter. -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 28 Mar '17

28 Mar '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/18557/12/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi.h: Line 87: #define SPIBAR_HSFSTS_W1C_BITS (0xff) > Because something is being directly used now does not mean it should be. If Got it. So, I will take a two step approach on this - 1) To split these register definition MACROs and move them to a different header file which will be only included from fast_spi.c. 2) Make an API call to this common code for every place wherever the registers are used from User side. -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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coreboot-gerrit March 2017