Martin Roth has posted comments on this change. ( https://review.coreboot.org/18905 )
Change subject: mainboard/neoware/g170: disable use of upper memory for SeaBIOS
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Patch Set 1:
You need a signed-off-by line in the commit message:
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
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Gerrit-MessageType: comment
Gerrit-Change-Id: I69f1fe38503b0f8d6015b515637d8376726490c0
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-HasComments: No
Hello build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18305
to look at the new patch set (#29).
Change subject: nb/i945/raminit: Use common ddr2 decode functions
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nb/i945/raminit: Use common ddr2 decode functions
This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31.
The result of this is that dimms with multiple asymmetric ranks are
not supported anymore. These however are very rare and most likely
never tested on this platform.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
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M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/i945/raminit.h
2 files changed, 149 insertions(+), 616 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/18305/29
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Gerrit-PatchSet: 29
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)
Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18320
to look at the new patch set (#22).
Change subject: device/dram/ddr2: Add functions to select common CAS en freq
......................................................................
device/dram/ddr2: Add functions to select common CAS en freq
This adds two functions:
- one to find the highest common tCLK per CAS;
- another to find to select tCLK and CAS based on the results of the
previous function and the limits on minimal tCLK the memory controller
can impose.
Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/device/dram/ddr2.c
M src/include/device/dram/ddr2.h
2 files changed, 83 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/18320/22
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e
Gerrit-PatchSet: 22
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins)